mirror of https://github.com/hak5/openwrt.git
115 lines
2.6 KiB
C
115 lines
2.6 KiB
C
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/*
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* Atheros AP91 reference board PCI initialization
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*
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/pci.h>
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#include <linux/ath9k_platform.h>
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#include <linux/delay.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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#include <asm/mach-ar71xx/pci.h>
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#include "dev-ap91-pci.h"
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static struct ath9k_platform_data ap91_wmac_data;
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static char ap91_wmac_mac[6];
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static int ap91_pci_fixup_enabled;
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static struct ar71xx_pci_irq ap91_pci_irqs[] __initdata = {
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{
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.slot = 0,
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.pin = 1,
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.irq = AR71XX_PCI_IRQ_DEV0,
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}
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};
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static int ap91_pci_plat_dev_init(struct pci_dev *dev)
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{
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switch(PCI_SLOT(dev->devfn)) {
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case 0:
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dev->dev.platform_data = &ap91_wmac_data;
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break;
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}
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return 0;
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}
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static void ap91_pci_fixup(struct pci_dev *dev)
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{
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void __iomem *mem;
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u16 *cal_data;
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u16 cmd;
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u32 val;
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if (!ap91_pci_fixup_enabled)
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return;
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printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev));
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cal_data = ap91_wmac_data.eeprom_data;
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if (*cal_data != 0xa55a) {
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printk(KERN_ERR "PCI: no calibration data found for %s\n",
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pci_name(dev));
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return;
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}
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mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000);
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if (!mem) {
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printk(KERN_ERR "PCI: ioremap error for device %s\n",
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pci_name(dev));
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return;
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}
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/* Setup the PCI device to allow access to the internal registers */
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff);
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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/* set pointer to first reg address */
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cal_data += 3;
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while (*cal_data != 0xffff) {
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u32 reg;
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reg = *cal_data++;
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val = *cal_data++;
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val |= (*cal_data++) << 16;
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__raw_writel(val, mem + reg);
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udelay(100);
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}
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pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
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dev->vendor = val & 0xffff;
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dev->device = (val >> 16) & 0xffff;
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pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
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dev->revision = val & 0xff;
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dev->class = val >> 8; /* upper 3 bytes */
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iounmap(mem);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ap91_pci_fixup);
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void __init ap91_pci_init(u8 *cal_data, u8 *mac_addr)
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{
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if (cal_data)
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memcpy(ap91_wmac_data.eeprom_data, cal_data,
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sizeof(ap91_wmac_data.eeprom_data));
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if (mac_addr) {
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memcpy(ap91_wmac_mac, mac_addr, sizeof(ap91_wmac_mac));
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ap91_wmac_data.macaddr = ap91_wmac_mac;
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}
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ar71xx_pci_plat_dev_init = ap91_pci_plat_dev_init;
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ar71xx_pci_init(ARRAY_SIZE(ap91_pci_irqs), ap91_pci_irqs);
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ap91_pci_fixup_enabled = 1;
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}
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