mirror of https://github.com/hak5/openwrt.git
233 lines
8.1 KiB
C
233 lines
8.1 KiB
C
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/******************************************************************************
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Copyright (c) 2004, Infineon Technologies. All rights reserved.
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No Warranty
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Because the program is licensed free of charge, there is no warranty for
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the program, to the extent permitted by applicable law. Except when
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otherwise stated in writing the copyright holders and/or other parties
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provide the program "as is" without warranty of any kind, either
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expressed or implied, including, but not limited to, the implied
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warranties of merchantability and fitness for a particular purpose. The
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entire risk as to the quality and performance of the program is with
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you. should the program prove defective, you assume the cost of all
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necessary servicing, repair or correction.
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In no event unless required by applicable law or agreed to in writing
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will any copyright holder, or any other party who may modify and/or
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redistribute the program as permitted above, be liable to you for
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damages, including any general, special, incidental or consequential
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damages arising out of the use or inability to use the program
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(including but not limited to loss of data or data being rendered
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inaccurate or losses sustained by you or third parties or a failure of
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the program to operate with any other programs), even if such holder or
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other party has been advised of the possibility of such damages.
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******************************************************************************
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Module : ifx_swdrv.h
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Date : 2004-09-01
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Description : JoeLin
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Remarks:
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*****************************************************************************/
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#ifndef _ADM_6996_MODULE_H_
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#define _ADM_6996_MODULE_H_
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#include <asm/amazon/amazon.h>
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#define ifx_printf(x) printk x
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/* command codes */
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#define ADM_SW_SMI_READ 0x02
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#define ADM_SW_SMI_WRITE 0x01
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#define ADM_SW_SMI_START 0x01
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#define ADM_SW_EEPROM_WRITE 0x01
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#define ADM_SW_EEPROM_WRITE_ENABLE 0x03
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#define ADM_SW_EEPROM_WRITE_DISABLE 0x00
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#define EEPROM_TYPE 8 /* for 93C66 */
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/* bit masks */
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#define ADM_SW_BIT_MASK_1 0x00000001
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#define ADM_SW_BIT_MASK_2 0x00000002
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#define ADM_SW_BIT_MASK_4 0x00000008
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#define ADM_SW_BIT_MASK_10 0x00000200
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#define ADM_SW_BIT_MASK_16 0x00008000
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#define ADM_SW_BIT_MASK_32 0x80000000
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/* delay timers */
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#define ADM_SW_MDC_DOWN_DELAY 5
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#define ADM_SW_MDC_UP_DELAY 5
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#define ADM_SW_CS_DELAY 5
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/* MDIO modes */
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#define ADM_SW_MDIO_OUTPUT 1
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#define ADM_SW_MDIO_INPUT 0
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#define ADM_SW_MAX_PORT_NUM 5
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#define ADM_SW_MAX_VLAN_NUM 15
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/* registers */
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#define ADM_SW_PORT0_CONF 0x1
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#define ADM_SW_PORT1_CONF 0x3
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#define ADM_SW_PORT2_CONF 0x5
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#define ADM_SW_PORT3_CONF 0x7
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#define ADM_SW_PORT4_CONF 0x8
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#define ADM_SW_PORT5_CONF 0x9
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#define ADM_SW_VLAN_MODE 0x11
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#define ADM_SW_MAC_LOCK 0x12
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#define ADM_SW_VLAN0_CONF 0x13
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#define ADM_SW_PORT0_PVID 0x28
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#define ADM_SW_PORT1_PVID 0x29
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#define ADM_SW_PORT2_PVID 0x2a
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#define ADM_SW_PORT34_PVID 0x2b
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#define ADM_SW_PORT5_PVID 0x2c
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#define ADM_SW_PHY_RESET 0x2f
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#define ADM_SW_MISC_CONF 0x30
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#define ADM_SW_BNDWDH_CTL0 0x31
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#define ADM_SW_BNDWDH_CTL1 0x32
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#define ADM_SW_BNDWDH_CTL_ENA 0x33
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/* port modes */
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#define ADM_SW_PORT_FLOWCTL 0x1 /* 802.3x flow control */
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#define ADM_SW_PORT_AN 0x2 /* auto negotiation */
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#define ADM_SW_PORT_100M 0x4 /* 100M */
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#define ADM_SW_PORT_FULL 0x8 /* full duplex */
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#define ADM_SW_PORT_TAG 0x10 /* output tag on */
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#define ADM_SW_PORT_DISABLE 0x20 /* disable port */
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#define ADM_SW_PORT_TOS 0x40 /* TOS first */
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#define ADM_SW_PORT_PPRI 0x80 /* port based priority first */
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#define ADM_SW_PORT_MDIX 0x8000 /* auto MDIX on */
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#define ADM_SW_PORT_PVID_SHIFT 10
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#define ADM_SW_PORT_PVID_BITS 4
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/* VLAN */
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#define ADM_SW_VLAN_PORT0 0x1
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#define ADM_SW_VLAN_PORT1 0x2
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#define ADM_SW_VLAN_PORT2 0x10
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#define ADM_SW_VLAN_PORT3 0x40
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#define ADM_SW_VLAN_PORT4 0x80
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#define ADM_SW_VLAN_PORT5 0x100
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/* GPIO 012 enabled, output mode */
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#define GPIO_ENABLEBITS 0x000700f8
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/*
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define AMAZON GPIO port to ADM6996 EEPROM interface
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MDIO -> EEDI GPIO 16, AMAZON GPIO P1.0, bi-direction
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MDC -> EESK GPIO 17, AMAZON GPIO P1.1, output only
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MDCS -> EECS GPIO 18, AMAZON GPIO P1.2, output only
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EEDO GPIO 15, AMAZON GPIO P0.15, do not need this one! */
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#define GPIO_MDIO 1 //P1.0
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#define GPIO_MDC 2 //P1.1
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#define GPIO_MDCS 4 //P1.2
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//joelin #define GPIO_MDIO 0
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//joelin #define GPIO_MDC 5 /* PORT 0 GPIO5 */
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//joelin #define GPIO_MDCS 6 /* PORT 0 GPIO6 */
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#define MDIO_INPUT 0x00000001
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#define MDIO_OUTPUT_EN 0x00010000
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/* type definitions */
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typedef unsigned char U8;
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typedef unsigned short U16;
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typedef unsigned int U32;
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typedef struct _REGRW_
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{
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unsigned int addr;
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unsigned int value;
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unsigned int mode;
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}REGRW, *PREGRW;
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//joelin adm6996i
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typedef struct _MACENTRY_
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{
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unsigned char mac_addr[6];
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unsigned long fid:4;
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unsigned long portmap:6;
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union {
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unsigned long age_timer:9;
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unsigned long info_ctrl:9;
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} ctrl;
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unsigned long occupy:1;
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unsigned long info_type:1;
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unsigned long bad:1;
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unsigned long result:3;//000:command ok ,001:all entry used,010:Entry Not found ,011:try next entry ,101:command error
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}MACENTRY, *PMACENTRY;
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typedef struct _PROTOCOLFILTER_
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{
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int protocol_filter_num;//[0~7]
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int ip_p; //Value Compared with Protocol in IP Heade[7:0]
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char action:2;//Action for protocol Filter .
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//00 = Protocol Portmap is Default Output Ports.
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//01 = Protocol Portmap is 6'b0.
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//10 = Protocol Portmap is the CPU port if the incoming port
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//is not the CPU port. But if the incoming port is the CPU port, then Type Portmap contains Default Output Ports, excluding the CPU port.
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}PROTOCOLFILTER, *PPROTOCOLFILTER;
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//joelin adm6996i
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/* Santosh: for IGMP proxy/snooping */
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//050614:fchang int adm_process_mac_table_request (unsigned int cmd, struct _MACENTRY_ *mac);
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//050614:fchang int adm_process_protocol_filter_request (unsigned int cmd, struct _PROTOCOLFILTER_ *filter);
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/* IOCTL keys */
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#define KEY_IOCTL_ADM_REGRW 0x01
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#define KEY_IOCTL_ADM_SW_REGRW 0x02
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#define KEY_IOCTL_ADM_SW_PORTSTS 0x03
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#define KEY_IOCTL_ADM_SW_INIT 0x04
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//for adm6996i-start
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#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD 0x05
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#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL 0x06
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#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT 0x07
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#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE 0x08
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#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD 0x09
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#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL 0x0a
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#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET 0x0b
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//adm6996i #define KEY_IOCTL_MAX_KEY 0x05
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#define KEY_IOCTL_MAX_KEY 0x0c
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//for adm6996i-end
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/* IOCTL MAGIC */
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#define ADM_MAGIC ('a'|'d'|'m'|'t'|'e'|'k')
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/* IOCTL parameters */
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#define ADM_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_REGRW, REGRW)
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#define ADM_SW_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_REGRW, REGRW)
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#define ADM_SW_IOCTL_PORTSTS _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_PORTSTS, NULL)
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#define ADM_SW_IOCTL_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_INIT, NULL)
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//6996i-stat
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#define ADM_SW_IOCTL_MACENTRY_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD,MACENTRY)
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#define ADM_SW_IOCTL_MACENTRY_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL,MACENTRY)
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#define ADM_SW_IOCTL_MACENTRY_GET_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT,MACENTRY)
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#define ADM_SW_IOCTL_MACENTRY_GET_MORE _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE,MACENTRY)
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#define ADM_SW_IOCTL_FILTER_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD,PROTOCOLFILTER)
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#define ADM_SW_IOCTL_FILTER_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL,PROTOCOLFILTER)
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#define ADM_SW_IOCTL_FILTER_GET _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET,PROTOCOLFILTER)
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//6996i-end
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#define REG_READ 0x0
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#define REG_WRITE 0x1
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/* undefine symbol */
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#define AMAZON_SW_REG(reg) *((volatile U32*)(reg))
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//#define GPIO0_INPUT_MASK 0
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//#define GPIO_conf0_REG 0x12345678
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//#define GPIO_SET_HI
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//#define GPIO_SET_LOW
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#endif
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/* _ADM_6996_MODULE_H_ */
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