mirror of https://github.com/hak5/openwrt.git
558 lines
14 KiB
Diff
558 lines
14 KiB
Diff
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From feb12cb699adbac2d4619401c7ff4fcc2fc97b6c Mon Sep 17 00:00:00 2001
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From: Mingkai Hu <mingkai.hu@nxp.com>
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Date: Mon, 26 Sep 2016 12:33:42 +0800
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Subject: [PATCH 132/141] dts/ls1046a: add LS1046ARDB board support
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commit e95a28cfd9a392fe5dc189a9ae097bbaaccd1228
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[context adjustment]
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Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
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Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
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---
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arch/arm64/boot/dts/freescale/Makefile | 1 +
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arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 198 +++++++++++++++++++++
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arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 178 +++++++++++++-----
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3 files changed, 328 insertions(+), 49 deletions(-)
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
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--- a/arch/arm64/boot/dts/freescale/Makefile
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+++ b/arch/arm64/boot/dts/freescale/Makefile
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@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
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+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
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@@ -0,0 +1,198 @@
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+/*
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+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
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+ *
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+ * Copyright 2016, Freescale Semiconductor
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+ *
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+ * Mingkai Hu <mingkai.hu@nxp.com>
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+ *
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+ * This file is dual-licensed: you can use it either under the terms
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+ * of the GPLv2 or the X11 license, at your option. Note that this dual
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+ * licensing only applies to this file, and not this project as a
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+ * whole.
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+ *
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+ * a) This library is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of the
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+ * License, or (at your option) any later version.
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+ *
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+ * This library is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Or, alternatively,
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+ *
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+ * b) Permission is hereby granted, free of charge, to any person
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+ * obtaining a copy of this software and associated documentation
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+ * files (the "Software"), to deal in the Software without
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+ * restriction, including without limitation the rights to use,
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+ * copy, modify, merge, publish, distribute, sublicense, and/or
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+ * sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following
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+ * conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be
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+ * included in all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+
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+/dts-v1/;
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+#include "fsl-ls1046a.dtsi"
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+
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+/ {
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+ model = "LS1046A RDB Board";
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+ compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
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+
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+ aliases {
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+ ethernet0 = &fm1mac3;
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+ ethernet1 = &fm1mac4;
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+ ethernet2 = &fm1mac5;
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+ ethernet3 = &fm1mac6;
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+ ethernet4 = &fm1mac9;
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+ ethernet5 = &fm1mac10;
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+ };
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+};
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+
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+&i2c0 {
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+ status = "okay";
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+ ina220@40 {
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+ compatible = "ti,ina220";
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+ reg = <0x40>;
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+ shunt-resistor = <1000>;
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+ };
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+ adt7461a@4c {
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+ compatible = "adi,adt7461";
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+ reg = <0x4c>;
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+ };
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+ eeprom@56 {
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+ compatible = "at24,24c512";
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+ reg = <0x52>;
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+ };
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+ eeprom@57 {
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+ compatible = "at24,24c512";
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+ reg = <0x53>;
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+ };
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+};
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+
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+&i2c3 {
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+ status = "okay";
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+ rtc@51 {
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+ compatible = "nxp,pcf2129";
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+ reg = <0x51>;
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+ };
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+};
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+
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+&ifc {
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+ status = "okay";
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ /* NAND Flashe and CPLD on board */
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+ ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
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+ 0x2 0x0 0x0 0x7fb00000 0x00000100>;
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+
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+ nand@0,0 {
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+ compatible = "fsl,ifc-nand";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ reg = <0x0 0x0 0x10000>;
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+ };
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+
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+ cpld: board-control@2,0 {
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+ compatible = "fsl,ls1046ardb-cpld";
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+ reg = <0x2 0x0 0x0000100>;
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+ };
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+};
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+
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+&qspi {
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+ num-cs = <2>;
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+ bus-num = <0>;
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+ status = "okay";
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+
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+ qflash0: s25fs128s@0 {
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+ compatible = "spansion,m25p80";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <20000000>;
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+ reg = <0>;
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+ };
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+
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+ qflash1: s25fs128s@1 {
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+ compatible = "spansion,m25p80";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <20000000>;
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+ reg = <1>;
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+ };
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+
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+};
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+
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+&duart0 {
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+ status = "okay";
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+};
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+
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+&duart1 {
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+ status = "okay";
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+};
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+
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+&fman0 {
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+ ethernet@e4000 {
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+ phy-handle = <&rgmii_phy1>;
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+ phy-connection-type = "rgmii";
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+ };
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+
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+ ethernet@e6000 {
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+ phy-handle = <&rgmii_phy2>;
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+ phy-connection-type = "rgmii";
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+ };
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+
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+ ethernet@e8000 {
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+ phy-handle = <&sgmii_phy1>;
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+ phy-connection-type = "sgmii";
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+ };
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+
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+ ethernet@ea000 {
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+ phy-handle = <&sgmii_phy2>;
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+ phy-connection-type = "sgmii";
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+ };
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+
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+ ethernet@f0000 { /* 10GEC1 */
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+ phy-handle = <&aqr106_phy>;
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+ phy-connection-type = "xgmii";
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+ };
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+
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+ ethernet@f2000 { /* 10GEC2 */
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+ fixed-link = <0 1 10000 0 0>;
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+ phy-connection-type = "xgmii";
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+ };
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+
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+ mdio@fc000 {
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+ rgmii_phy1: ethernet-phy@1 {
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+ reg = <0x1>;
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+ };
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+ rgmii_phy2: ethernet-phy@2 {
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+ reg = <0x2>;
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+ };
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+ sgmii_phy1: ethernet-phy@3 {
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+ reg = <0x3>;
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+ };
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+ sgmii_phy2: ethernet-phy@4 {
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+ reg = <0x4>;
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+ };
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+ };
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+
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+ mdio@fd000 {
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+ aqr106_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ interrupts = <0 131 4>;
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+ reg = <0x0>;
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+ };
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+ };
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+};
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
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@@ -51,13 +51,7 @@
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#size-cells = <2>;
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aliases {
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- ethernet0 = &fm1mac1;
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- ethernet1 = &fm1mac2;
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- ethernet2 = &fm1mac3;
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- ethernet3 = &fm1mac4;
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- ethernet4 = &fm1mac5;
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- ethernet5 = &fm1mac6;
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- ethernet6 = &fm1mac9;
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+ crypto = &crypto;
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};
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cpus {
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@@ -70,6 +64,7 @@
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reg = <0x0>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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+ cpu-idle-states = <&CPU_PH20>;
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};
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cpu1: cpu@1 {
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@@ -78,6 +73,7 @@
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reg = <0x1>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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+ cpu-idle-states = <&CPU_PH20>;
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};
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cpu2: cpu@2 {
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@@ -86,6 +82,7 @@
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reg = <0x2>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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+ cpu-idle-states = <&CPU_PH20>;
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};
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cpu3: cpu@3 {
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@@ -94,6 +91,7 @@
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reg = <0x3>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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+ cpu-idle-states = <&CPU_PH20>;
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};
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l2: l2-cache {
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@@ -101,6 +99,19 @@
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};
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};
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+ idle-states {
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+ entry-method = "arm,psci";
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+
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+ CPU_PH20: cpu-ph20 {
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+ compatible = "arm,idle-state";
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+ idle-state-name = "PH20";
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+ arm,psci-suspend-param = <0x00010000>;
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+ entry-latency-us = <1000>;
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+ exit-latency-us = <1000>;
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+ min-residency-us = <3000>;
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+ };
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+ };
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+
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0 0x80000000>;
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@@ -193,6 +204,49 @@
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bus-width = <4>;
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};
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+ crypto: crypto@1700000 {
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+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
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+ "fsl,sec-v4.0";
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+ fsl,sec-era = <8>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0x0 0x00 0x1700000 0x100000>;
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+ reg = <0x00 0x1700000 0x0 0x100000>;
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+ interrupts = <0 75 0x4>;
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+
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+ sec_jr0: jr@10000 {
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+ compatible = "fsl,sec-v5.4-job-ring",
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+ "fsl,sec-v5.0-job-ring",
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+ "fsl,sec-v4.0-job-ring";
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+ reg = <0x10000 0x10000>;
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+ interrupts = <0 71 0x4>;
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+ };
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+
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+ sec_jr1: jr@20000 {
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+ compatible = "fsl,sec-v5.4-job-ring",
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+ "fsl,sec-v5.0-job-ring",
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+ "fsl,sec-v4.0-job-ring";
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+ reg = <0x20000 0x10000>;
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+ interrupts = <0 72 0x4>;
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+ };
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+
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+ sec_jr2: jr@30000 {
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+ compatible = "fsl,sec-v5.4-job-ring",
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+ "fsl,sec-v5.0-job-ring",
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+ "fsl,sec-v4.0-job-ring";
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+ reg = <0x30000 0x10000>;
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+ interrupts = <0 73 0x4>;
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+ };
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+
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+ sec_jr3: jr@40000 {
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+ compatible = "fsl,sec-v5.4-job-ring",
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+ "fsl,sec-v5.0-job-ring",
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+ "fsl,sec-v4.0-job-ring";
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+ reg = <0x40000 0x10000>;
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+ interrupts = <0 74 0x4>;
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+ };
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+ };
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+
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qman: qman@1880000 {
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compatible = "fsl,qman";
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reg = <0x00 0x1880000 0x0 0x10000>;
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@@ -490,6 +544,19 @@
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fsl,qman-channel-id = <0x800>;
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};
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+ fman0_10g_rx1: port@91000 {
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+ cell-index = <1>;
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+ compatible = "fsl,fman-port-10g-rx";
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+ reg = <0x91000 0x1000>;
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+ };
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+
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+ fman0_10g_tx1: port@b1000 {
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+ cell-index = <1>;
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+ compatible = "fsl,fman-port-10g-tx";
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+ reg = <0xb1000 0x1000>;
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+ fsl,qman-channel-id = <0x801>;
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+ };
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+
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fm1mac9: ethernet@f0000 {
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cell-index = <0>;
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compatible = "fsl,fman-memac";
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@@ -497,6 +564,13 @@
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fsl,port-handles = <&fman0_10g_rx0 &fman0_10g_tx0>;
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};
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+ fm1mac10: ethernet@f2000 {
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+ cell-index = <1>;
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+ compatible = "fsl,fman-memac";
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+ reg = <0xf2000 0x1000>;
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+ fsl,port-handles = <&fman0_10g_rx1 &fman0_10g_tx1>;
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+ };
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+
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mdio@f1000 {
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -504,6 +578,13 @@
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reg = <0xf1000 0x1000>;
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};
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+ mdio@f3000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "fsl,fman-memac-mdio";
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+ reg = <0xf3000 0x1000>;
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+ };
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+
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ptp_timer0: rtc@fe000 {
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compatible = "fsl,fman-rtc";
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reg = <0xfe000 0x1000>;
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@@ -657,7 +738,7 @@
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2950000 0x0 0x1000>;
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interrupts = <0 48 0x4>;
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- clocks = <&clockgen 0 0>;
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+ clocks = <&clockgen 4 0>;
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clock-names = "ipg";
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status = "disabled";
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};
|
||
|
@@ -712,7 +793,7 @@
|
||
|
reg = <0x0 0x29d0000 0x0 0x10000>;
|
||
|
interrupts = <0 86 0x4>;
|
||
|
big-endian;
|
||
|
- rcpm-wakeup = <&rcpm 0x0 0x20000000>;
|
||
|
+ rcpm-wakeup = <&rcpm 0x00020000 0x0>;
|
||
|
status = "okay";
|
||
|
};
|
||
|
|
||
|
@@ -789,34 +870,34 @@
|
||
|
big-endian;
|
||
|
};
|
||
|
|
||
|
- msi1: msi-controller@1580000 {
|
||
|
- compatible = "fsl,1s1046a-msi";
|
||
|
- reg = <0x0 0x1580000 0x0 0x10000>;
|
||
|
+ msi: msi-controller@1580000 {
|
||
|
+ compatible = "fsl,ls1046a-msi";
|
||
|
+ #address-cells = <2>;
|
||
|
+ #size-cells = <2>;
|
||
|
+ ranges;
|
||
|
msi-controller;
|
||
|
- interrupts = <0 116 0x4>,
|
||
|
- <0 111 0x4>,
|
||
|
- <0 112 0x4>,
|
||
|
- <0 113 0x4>;
|
||
|
- };
|
||
|
|
||
|
- msi2: msi-controller@1590000 {
|
||
|
- compatible = "fsl,1s1046a-msi";
|
||
|
- reg = <0x0 0x1590000 0x0 0x10000>;
|
||
|
- msi-controller;
|
||
|
- interrupts = <0 126 0x4>,
|
||
|
- <0 121 0x4>,
|
||
|
- <0 122 0x4>,
|
||
|
- <0 123 0x4>;
|
||
|
- };
|
||
|
-
|
||
|
- msi3: msi-controller@15a0000 {
|
||
|
- compatible = "fsl,1s1046a-msi";
|
||
|
- reg = <0x0 0x15a0000 0x0 0x10000>;
|
||
|
- msi-controller;
|
||
|
- interrupts = <0 160 0x4>,
|
||
|
- <0 155 0x4>,
|
||
|
- <0 156 0x4>,
|
||
|
- <0 157 0x4>;
|
||
|
+ msi-bank@1580000 {
|
||
|
+ reg = <0x0 0x1580000 0x0 0x10000>;
|
||
|
+ interrupts = <0 116 0x4>,
|
||
|
+ <0 111 0x4>,
|
||
|
+ <0 112 0x4>,
|
||
|
+ <0 113 0x4>;
|
||
|
+ };
|
||
|
+ msi-bank@1590000 {
|
||
|
+ reg = <0x0 0x1590000 0x0 0x10000>;
|
||
|
+ interrupts = <0 126 0x4>,
|
||
|
+ <0 121 0x4>,
|
||
|
+ <0 122 0x4>,
|
||
|
+ <0 123 0x4>;
|
||
|
+ };
|
||
|
+ msi-bank@15a0000 {
|
||
|
+ reg = <0x0 0x15a0000 0x0 0x10000>;
|
||
|
+ interrupts = <0 160 0x4>,
|
||
|
+ <0 155 0x4>,
|
||
|
+ <0 156 0x4>,
|
||
|
+ <0 157 0x4>;
|
||
|
+ };
|
||
|
};
|
||
|
|
||
|
pcie@3400000 {
|
||
|
@@ -826,15 +907,16 @@
|
||
|
reg-names = "regs", "config";
|
||
|
interrupts = <0 118 0x4>, /* controller interrupt */
|
||
|
<0 117 0x4>; /* PME interrupt */
|
||
|
- interrupt-names = "intr", "pme";
|
||
|
+ interrupt-names = "aer";
|
||
|
#address-cells = <3>;
|
||
|
#size-cells = <2>;
|
||
|
device_type = "pci";
|
||
|
+ dma-coherent;
|
||
|
num-lanes = <4>;
|
||
|
bus-range = <0x0 0xff>;
|
||
|
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||
|
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||
|
- msi-parent = <&msi1>;
|
||
|
+ msi-parent = <&msi>;
|
||
|
#interrupt-cells = <1>;
|
||
|
interrupt-map-mask = <0 0 0 7>;
|
||
|
interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
|
||
|
@@ -850,15 +932,16 @@
|
||
|
reg-names = "regs", "config";
|
||
|
interrupts = <0 128 0x4>,
|
||
|
<0 127 0x4>;
|
||
|
- interrupt-names = "intr", "pme";
|
||
|
+ interrupt-names = "aer";
|
||
|
#address-cells = <3>;
|
||
|
#size-cells = <2>;
|
||
|
device_type = "pci";
|
||
|
+ dma-coherent;
|
||
|
num-lanes = <2>;
|
||
|
bus-range = <0x0 0xff>;
|
||
|
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||
|
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||
|
- msi-parent = <&msi2>;
|
||
|
+ msi-parent = <&msi>;
|
||
|
#interrupt-cells = <1>;
|
||
|
interrupt-map-mask = <0 0 0 7>;
|
||
|
interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
|
||
|
@@ -874,15 +957,16 @@
|
||
|
reg-names = "regs", "config";
|
||
|
interrupts = <0 162 0x4>,
|
||
|
<0 161 0x4>;
|
||
|
- interrupt-names = "intr", "pme";
|
||
|
+ interrupt-names = "aer";
|
||
|
#address-cells = <3>;
|
||
|
#size-cells = <2>;
|
||
|
device_type = "pci";
|
||
|
+ dma-coherent;
|
||
|
num-lanes = <2>;
|
||
|
bus-range = <0x0 0xff>;
|
||
|
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||
|
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||
|
- msi-parent = <&msi3>;
|
||
|
+ msi-parent = <&msi>;
|
||
|
#interrupt-cells = <1>;
|
||
|
interrupt-map-mask = <0 0 0 7>;
|
||
|
interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
|
||
|
@@ -894,14 +978,6 @@
|
||
|
|
||
|
fsl,dpaa {
|
||
|
compatible = "fsl,ls1046a-dpaa", "simple-bus", "fsl,dpaa";
|
||
|
- ethernet@0 {
|
||
|
- compatible = "fsl,dpa-ethernet";
|
||
|
- fsl,fman-mac = <&fm1mac1>;
|
||
|
- };
|
||
|
- ethernet@1 {
|
||
|
- compatible = "fsl,dpa-ethernet";
|
||
|
- fsl,fman-mac = <&fm1mac2>;
|
||
|
- };
|
||
|
ethernet@2 {
|
||
|
compatible = "fsl,dpa-ethernet";
|
||
|
fsl,fman-mac = <&fm1mac3>;
|
||
|
@@ -922,6 +998,10 @@
|
||
|
compatible = "fsl,dpa-ethernet";
|
||
|
fsl,fman-mac = <&fm1mac9>;
|
||
|
};
|
||
|
+ ethernet@9 {
|
||
|
+ compatible = "fsl,dpa-ethernet";
|
||
|
+ fsl,fman-mac = <&fm1mac10>;
|
||
|
+ };
|
||
|
};
|
||
|
|
||
|
qportals: qman-portals@500000000 {
|