mirror of https://github.com/hak5/openwrt.git
129 lines
2.5 KiB
Diff
129 lines
2.5 KiB
Diff
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From eeacc2529942051504bc957726aa178671344421 Mon Sep 17 00:00:00 2001
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From: Maxime Bizon <mbizon@freebox.fr>
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Date: Wed, 20 Jan 2010 16:21:30 +0100
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Subject: [PATCH 32/63] bcm63xx: add support for 96368MVWG board.
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---
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arch/mips/bcm63xx/boards/board_bcm963xx.c | 95 ++++++++++++++++++++
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.../mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 2 +
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2 files changed, 97 insertions(+), 0 deletions(-)
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--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
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+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
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@@ -2225,6 +2225,78 @@ static struct board_info __initdata boar
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#endif
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/*
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+ * known 6368 boards
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+ */
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+#ifdef CONFIG_BCM63XX_CPU_6368
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+static struct board_info __initdata board_96368mvwg = {
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+ .name = "96368MVWG",
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+ .expected_cpu_id = 0x6368,
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+
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+ .has_uart0 = 1,
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+ .has_pci = 1,
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+ .has_enetsw = 1,
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+
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+ .enetsw = {
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+ .used_ports = {
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+ [1] = {
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+ .used = 1,
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+ .phy_id = 2,
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+ .name = "port1",
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+ },
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+
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+ [2] = {
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+ .used = 1,
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+ .phy_id = 3,
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+ .name = "port2",
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+ },
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+
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+ [4] = {
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+ .used = 1,
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+ .phy_id = 0x12,
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+ .name = "port0",
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+ },
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+
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+ [5] = {
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+ .used = 1,
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+ .phy_id = 0x11,
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+ .name = "port3",
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+ },
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+ },
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+ },
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+
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+ .leds = {
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+ {
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+ .name = "96368MVWG:green:adsl",
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+ .gpio = 2,
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+ .active_low = 1,
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+ },
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+ {
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+ .name = "96368MVWG:green:ppp",
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+ .gpio = 5,
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+ },
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+ {
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+ .name = "96368MVWG:green:power",
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+ .gpio = 22,
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+ .active_low = 1,
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+ .default_trigger = "default-on",
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+ },
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+ {
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+ .name = "96368MVWG:green:wps",
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+ .gpio = 23,
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+ .active_low = 1,
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+ },
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+ {
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+ .name = "96368MVWG:green:ppp-fail",
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+ .gpio = 31,
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+ },
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+ },
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+
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+ .has_ohci0 = 1,
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+ .has_ehci0 = 1,
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+};
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+#endif
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+
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+/*
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* all boards
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*/
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static const struct board_info __initconst *bcm963xx_boards[] = {
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@@ -2279,6 +2351,10 @@ static const struct board_info __initcon
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&board_HW553,
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&board_spw303v,
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#endif
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+
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+#ifdef CONFIG_BCM63XX_CPU_6368
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+ &board_96368mvwg,
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+#endif
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};
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/*
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@@ -2460,12 +2536,25 @@ void __init board_prom_init(void)
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bcm63xx_pci_enabled = 1;
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if (BCMCPU_IS_6348())
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val |= GPIO_MODE_6348_G2_PCI;
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+
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+ if (BCMCPU_IS_6368())
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+ val |= GPIO_MODE_6368_PCI_REQ1 |
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+ GPIO_MODE_6368_PCI_GNT1 |
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+ GPIO_MODE_6368_PCI_INTB |
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+ GPIO_MODE_6368_PCI_REQ0 |
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+ GPIO_MODE_6368_PCI_GNT0;
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}
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#endif
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if (board.has_pccard) {
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if (BCMCPU_IS_6348())
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val |= GPIO_MODE_6348_G1_MII_PCCARD;
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+
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+ if (BCMCPU_IS_6368())
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+ val |= GPIO_MODE_6368_PCMCIA_CD1 |
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+ GPIO_MODE_6368_PCMCIA_CD2 |
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+ GPIO_MODE_6368_PCMCIA_VS1 |
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+ GPIO_MODE_6368_PCMCIA_VS2;
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}
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if (board.has_enet0 && !board.enet0.use_internal_phy) {
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