mirror of https://github.com/hak5/openwrt.git
207 lines
6.0 KiB
Diff
207 lines
6.0 KiB
Diff
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From 8622d6da5d95293d474c156612fd819fdaf542ec Mon Sep 17 00:00:00 2001
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From: Kapil Hali <kapilh@broadcom.com>
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Date: Wed, 25 Nov 2015 08:58:53 -0500
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Subject: [PATCH 131/134] ARM: BCM: Clean up SMP support for Broadcom Kona
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These changes cleans up SMP implementaion for Broadcom's
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Kona SoC which are required for handling SMP for iProc
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family of SoCs at a single place for BCM NSP and BCM Kona.
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Signed-off-by: Kapil Hali <kapilh@broadcom.com>
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---
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arch/arm/boot/dts/bcm11351.dtsi | 2 +-
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arch/arm/boot/dts/bcm21664.dtsi | 2 +-
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arch/arm/mach-bcm/kona_smp.c | 82 +++++++++++++++++++++++++++--------------
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3 files changed, 56 insertions(+), 30 deletions(-)
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--- a/arch/arm/boot/dts/bcm11351.dtsi
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+++ b/arch/arm/boot/dts/bcm11351.dtsi
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@@ -31,7 +31,6 @@
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "brcm,bcm11351-cpu-method";
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- secondary-boot-reg = <0x3500417c>;
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cpu0: cpu@0 {
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device_type = "cpu";
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@@ -42,6 +41,7 @@
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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+ secondary-boot-reg = <0x3500417c>;
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reg = <1>;
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};
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};
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--- a/arch/arm/boot/dts/bcm21664.dtsi
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+++ b/arch/arm/boot/dts/bcm21664.dtsi
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@@ -31,7 +31,6 @@
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "brcm,bcm11351-cpu-method";
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- secondary-boot-reg = <0x35004178>;
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cpu0: cpu@0 {
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device_type = "cpu";
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@@ -42,6 +41,7 @@
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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+ secondary-boot-reg = <0x35004178>;
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reg = <1>;
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};
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};
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--- a/arch/arm/mach-bcm/kona_smp.c
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+++ b/arch/arm/mach-bcm/kona_smp.c
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@@ -1,5 +1,5 @@
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/*
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- * Copyright (C) 2014 Broadcom Corporation
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+ * Copyright (C) 2014-2015 Broadcom Corporation
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* Copyright 2014 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or
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@@ -30,9 +30,10 @@
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/* Name of device node property defining secondary boot register location */
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#define OF_SECONDARY_BOOT "secondary-boot-reg"
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+#define MPIDR_CPUID_BITMASK 0x3
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/* I/O address of register used to coordinate secondary core startup */
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-static u32 secondary_boot;
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+static u32 secondary_boot_addr;
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/*
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* Enable the Cortex A9 Snoop Control Unit
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@@ -78,44 +79,68 @@ static int __init scu_a9_enable(void)
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static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
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{
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static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
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- struct device_node *node;
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+ struct device_node *cpus_node = NULL;
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+ struct device_node *cpu_node = NULL;
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int ret;
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- BUG_ON(secondary_boot); /* We're called only once */
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-
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/*
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* This function is only called via smp_ops->smp_prepare_cpu().
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* That only happens if a "/cpus" device tree node exists
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* and has an "enable-method" property that selects the SMP
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* operations defined herein.
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*/
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- node = of_find_node_by_path("/cpus");
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- BUG_ON(!node);
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-
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- /*
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- * Our secondary enable method requires a "secondary-boot-reg"
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- * property to specify a register address used to request the
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- * ROM code boot a secondary code. If we have any trouble
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- * getting this we fall back to uniprocessor mode.
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- */
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- if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
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- pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
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- node->name);
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- ret = -ENOENT; /* Arrange to disable SMP */
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- goto out;
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+ cpus_node = of_find_node_by_path("/cpus");
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+ if (!cpus_node)
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+ return;
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+
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+ for_each_child_of_node(cpus_node, cpu_node) {
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+ u32 cpuid;
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+
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+ if (of_node_cmp(cpu_node->type, "cpu"))
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+ continue;
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+
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+ if (of_property_read_u32(cpu_node, "reg", &cpuid)) {
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+ pr_debug("%s: missing reg property\n",
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+ cpu_node->full_name);
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+ ret = -ENOENT;
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+ goto out;
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+ }
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+
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+ /*
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+ * "secondary-boot-reg" property should be defined only
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+ * for secondary cpu
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+ */
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+ if ((cpuid & MPIDR_CPUID_BITMASK) == 1) {
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+ /*
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+ * Our secondary enable method requires a
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+ * "secondary-boot-reg" property to specify a register
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+ * address used to request the ROM code boot a secondary
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+ * core. If we have any trouble getting this we fall
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+ * back to uniprocessor mode.
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+ */
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+ if (of_property_read_u32(cpu_node,
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+ OF_SECONDARY_BOOT,
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+ &secondary_boot_addr)) {
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+ pr_warn("%s: no" OF_SECONDARY_BOOT "property\n",
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+ cpu_node->name);
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+ ret = -ENOENT;
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+ goto out;
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+ }
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+ }
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}
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/*
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- * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
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+ * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
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* returned, the SoC reported a uniprocessor configuration.
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* We bail on any other error.
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*/
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ret = scu_a9_enable();
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out:
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- of_node_put(node);
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+ of_node_put(cpu_node);
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+ of_node_put(cpus_node);
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+
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if (ret) {
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/* Update the CPU present map to reflect uniprocessor mode */
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- BUG_ON(ret != -ENOENT);
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pr_warn("disabling SMP\n");
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init_cpu_present(&only_cpu_0);
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}
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@@ -139,7 +164,7 @@ out:
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* - Wait for the secondary boot register to be re-written, which
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* indicates the secondary core has started.
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*/
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-static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
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+static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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void __iomem *boot_reg;
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phys_addr_t boot_func;
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@@ -154,15 +179,16 @@ static int bcm_boot_secondary(unsigned i
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return -EINVAL;
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}
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- if (!secondary_boot) {
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+ if (!secondary_boot_addr) {
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pr_err("required secondary boot register not specified\n");
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return -EINVAL;
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}
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- boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32));
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+ boot_reg = ioremap_nocache(
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+ (phys_addr_t)secondary_boot_addr, sizeof(u32));
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if (!boot_reg) {
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pr_err("unable to map boot register for cpu %u\n", cpu_id);
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- return -ENOSYS;
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+ return -ENOMEM;
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}
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/*
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@@ -191,12 +217,12 @@ static int bcm_boot_secondary(unsigned i
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pr_err("timeout waiting for cpu %u to start\n", cpu_id);
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- return -ENOSYS;
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+ return -ENXIO;
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}
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static struct smp_operations bcm_smp_ops __initdata = {
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.smp_prepare_cpus = bcm_smp_prepare_cpus,
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- .smp_boot_secondary = bcm_boot_secondary,
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+ .smp_boot_secondary = kona_boot_secondary,
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};
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CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
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&bcm_smp_ops);
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