mirror of https://github.com/hak5/openwrt.git
48 lines
1.6 KiB
Diff
48 lines
1.6 KiB
Diff
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On Cortex-A9 based Marvell SoCs, when HW I/O coherency is enabled, all
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non-RAM space needs to be mapped strongly ordered.
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In upstream this was added for PCIe I/O only, this change expands it
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to cover all device memory. Fixes issues with CESA.
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Based on patch from Thomas Petazzoni.
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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--- a/arch/arm/mach-mvebu/coherency.c
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+++ b/arch/arm/mach-mvebu/coherency.c
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@@ -162,22 +162,16 @@ exit:
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}
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/*
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- * This ioremap hook is used on Armada 375/38x to ensure that PCIe
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+ * This ioremap hook is used on Armada 375/38x to ensure that all non-RAM
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* memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
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- * is needed as a workaround for a deadlock issue between the PCIe
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+ * is needed as a workaround for a deadlock issue between the bus
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* interface and the cache controller.
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*/
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static void __iomem *
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-armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
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- unsigned int mtype, void *caller)
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+armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
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+ unsigned int mtype, void *caller)
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{
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- struct resource pcie_mem;
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-
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- mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
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-
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- if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
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- mtype = MT_UNCACHED;
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-
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+ mtype = MT_UNCACHED;
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return __arm_ioremap_caller(phys_addr, size, mtype, caller);
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}
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@@ -186,7 +180,7 @@ static void __init armada_375_380_cohere
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struct device_node *cache_dn;
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coherency_cpu_base = of_iomap(np, 0);
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- arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
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+ arch_ioremap_caller = armada_wa_ioremap_caller;
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/*
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* We should switch the PL310 to I/O coherency mode only if
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