mirror of https://github.com/hak5/openwrt.git
275 lines
8.7 KiB
Diff
275 lines
8.7 KiB
Diff
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--- a/drivers/net/wireless/ath/ath9k/hw.c
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+++ b/drivers/net/wireless/ath/ath9k/hw.c
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@@ -684,14 +684,14 @@ static void ath9k_hw_init_qos(struct ath
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unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
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{
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- REG_WRITE(ah, PLL3, (REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK)));
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- udelay(100);
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- REG_WRITE(ah, PLL3, (REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK));
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+ REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
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+ udelay(100);
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+ REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
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- while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
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- udelay(100);
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+ while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
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+ udelay(100);
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- return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
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+ return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
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}
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EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
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@@ -841,8 +841,7 @@ void ath9k_hw_init_global_settings(struc
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ah->misc_mode);
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if (ah->misc_mode != 0)
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- REG_WRITE(ah, AR_PCU_MISC,
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- REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
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+ REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
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if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
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sifstime = 16;
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@@ -910,23 +909,19 @@ u32 ath9k_regd_get_ctl(struct ath_regula
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static inline void ath9k_hw_set_dma(struct ath_hw *ah)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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- u32 regval;
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ENABLE_REGWRITE_BUFFER(ah);
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/*
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* set AHB_MODE not to do cacheline prefetches
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*/
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- if (!AR_SREV_9300_20_OR_LATER(ah)) {
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- regval = REG_READ(ah, AR_AHB_MODE);
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- REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
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- }
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+ if (!AR_SREV_9300_20_OR_LATER(ah))
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+ REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
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/*
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* let mac dma reads be in 128 byte chunks
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*/
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- regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
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- REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
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+ REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
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REGWRITE_BUFFER_FLUSH(ah);
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@@ -943,8 +938,7 @@ static inline void ath9k_hw_set_dma(stru
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/*
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* let mac dma writes be in 128 byte chunks
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*/
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- regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
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- REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
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+ REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
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/*
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* Setup receive FIFO threshold to hold off TX activities
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@@ -983,30 +977,27 @@ static inline void ath9k_hw_set_dma(stru
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static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
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{
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- u32 val;
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+ u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
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+ u32 set = AR_STA_ID1_KSRCH_MODE;
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- val = REG_READ(ah, AR_STA_ID1);
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- val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
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switch (opmode) {
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- case NL80211_IFTYPE_AP:
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- REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
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- | AR_STA_ID1_KSRCH_MODE);
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- REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
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- break;
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case NL80211_IFTYPE_ADHOC:
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case NL80211_IFTYPE_MESH_POINT:
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- REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
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- | AR_STA_ID1_KSRCH_MODE);
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+ set |= AR_STA_ID1_ADHOC;
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REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
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break;
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+ case NL80211_IFTYPE_AP:
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+ set |= AR_STA_ID1_STA_AP;
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+ /* fall through */
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case NL80211_IFTYPE_STATION:
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- REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
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+ REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
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break;
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default:
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- if (ah->is_monitoring)
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- REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
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+ if (!ah->is_monitoring)
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+ set = 0;
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break;
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}
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+ REG_RMW(ah, AR_STA_ID1, set, mask);
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}
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void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
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@@ -1032,10 +1023,8 @@ static bool ath9k_hw_set_reset(struct at
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u32 tmpReg;
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if (AR_SREV_9100(ah)) {
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- u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
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- val &= ~AR_RTC_DERIVED_CLK_PERIOD;
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- val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
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- REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
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+ REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
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+ AR_RTC_DERIVED_CLK_PERIOD, 1);
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(void)REG_READ(ah, AR_RTC_DERIVED_CLK);
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}
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@@ -1460,8 +1449,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
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ar9002_hw_enable_wep_aggregation(ah);
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}
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- REG_WRITE(ah, AR_STA_ID1,
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- REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
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+ REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
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ath9k_hw_set_dma(ah);
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@@ -2213,11 +2201,9 @@ void ath9k_hw_setrxfilter(struct ath_hw
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REG_WRITE(ah, AR_PHY_ERR, phybits);
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if (phybits)
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- REG_WRITE(ah, AR_RXCFG,
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- REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
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+ REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
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else
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- REG_WRITE(ah, AR_RXCFG,
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- REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
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+ REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
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REGWRITE_BUFFER_FLUSH(ah);
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}
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--- a/drivers/net/wireless/ath/ath9k/mac.c
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+++ b/drivers/net/wireless/ath/ath9k/mac.c
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@@ -465,10 +465,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw
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REG_WRITE(ah, AR_QCBRCFG(q),
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SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
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SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
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- REG_WRITE(ah, AR_QMISC(q),
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- REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
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- (qi->tqi_cbrOverflowLimit ?
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- AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
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+ REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
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+ (qi->tqi_cbrOverflowLimit ?
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+ AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
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}
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if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
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REG_WRITE(ah, AR_QRDYTIMECFG(q),
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@@ -481,40 +480,31 @@ bool ath9k_hw_resettxqueue(struct ath_hw
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(qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
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if (qi->tqi_burstTime
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- && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
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- REG_WRITE(ah, AR_QMISC(q),
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- REG_READ(ah, AR_QMISC(q)) |
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- AR_Q_MISC_RDYTIME_EXP_POLICY);
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+ && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
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+ REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
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- }
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-
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- if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
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- REG_WRITE(ah, AR_DMISC(q),
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- REG_READ(ah, AR_DMISC(q)) |
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- AR_D_MISC_POST_FR_BKOFF_DIS);
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- }
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+ if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
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+ REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
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REGWRITE_BUFFER_FLUSH(ah);
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- if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
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- REG_WRITE(ah, AR_DMISC(q),
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- REG_READ(ah, AR_DMISC(q)) |
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- AR_D_MISC_FRAG_BKOFF_EN);
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- }
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+ if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
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+ REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
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+
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switch (qi->tqi_type) {
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case ATH9K_TX_QUEUE_BEACON:
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ENABLE_REGWRITE_BUFFER(ah);
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- REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
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- | AR_Q_MISC_FSP_DBA_GATED
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- | AR_Q_MISC_BEACON_USE
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- | AR_Q_MISC_CBR_INCR_DIS1);
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+ REG_SET_BIT(ah, AR_QMISC(q),
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+ AR_Q_MISC_FSP_DBA_GATED
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+ | AR_Q_MISC_BEACON_USE
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+ | AR_Q_MISC_CBR_INCR_DIS1);
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- REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
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- | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
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+ REG_SET_BIT(ah, AR_DMISC(q),
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+ (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
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AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
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- | AR_D_MISC_BEACON_USE
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- | AR_D_MISC_POST_FR_BKOFF_DIS);
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+ | AR_D_MISC_BEACON_USE
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+ | AR_D_MISC_POST_FR_BKOFF_DIS);
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REGWRITE_BUFFER_FLUSH(ah);
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@@ -533,41 +523,38 @@ bool ath9k_hw_resettxqueue(struct ath_hw
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case ATH9K_TX_QUEUE_CAB:
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ENABLE_REGWRITE_BUFFER(ah);
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- REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
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- | AR_Q_MISC_FSP_DBA_GATED
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- | AR_Q_MISC_CBR_INCR_DIS1
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- | AR_Q_MISC_CBR_INCR_DIS0);
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+ REG_SET_BIT(ah, AR_QMISC(q),
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+ AR_Q_MISC_FSP_DBA_GATED
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+ | AR_Q_MISC_CBR_INCR_DIS1
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+ | AR_Q_MISC_CBR_INCR_DIS0);
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value = (qi->tqi_readyTime -
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(ah->config.sw_beacon_response_time -
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ah->config.dma_beacon_response_time) -
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ah->config.additional_swba_backoff) * 1024;
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REG_WRITE(ah, AR_QRDYTIMECFG(q),
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value | AR_Q_RDYTIMECFG_EN);
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- REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
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- | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
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+ REG_SET_BIT(ah, AR_DMISC(q),
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+ (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
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AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
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REGWRITE_BUFFER_FLUSH(ah);
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break;
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case ATH9K_TX_QUEUE_PSPOLL:
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- REG_WRITE(ah, AR_QMISC(q),
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- REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
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+ REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
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break;
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case ATH9K_TX_QUEUE_UAPSD:
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- REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
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- AR_D_MISC_POST_FR_BKOFF_DIS);
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+ REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
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break;
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default:
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break;
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}
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if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
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- REG_WRITE(ah, AR_DMISC(q),
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- REG_READ(ah, AR_DMISC(q)) |
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- SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
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- AR_D_MISC_ARB_LOCKOUT_CNTRL) |
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- AR_D_MISC_POST_FR_BKOFF_DIS);
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+ REG_SET_BIT(ah, AR_DMISC(q),
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+ SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
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+ AR_D_MISC_ARB_LOCKOUT_CNTRL) |
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+ AR_D_MISC_POST_FR_BKOFF_DIS);
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}
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if (AR_SREV_9300_20_OR_LATER(ah))
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