mirror of https://github.com/hak5/openwrt.git
104 lines
2.8 KiB
Diff
104 lines
2.8 KiB
Diff
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From 1748dc7b4974109040d0249ac1fc322c120eb528 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 16 Mar 2012 15:49:32 +0100
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Subject: [PATCH 62/70] MIPS: cleanup reset code
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---
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arch/mips/lantiq/xway/reset.c | 59 ++++++++++++++++++++++++++++++++++------
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1 files changed, 50 insertions(+), 9 deletions(-)
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diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
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index ca2212a..8a5dff1 100644
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--- a/arch/mips/lantiq/xway/reset.c
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+++ b/arch/mips/lantiq/xway/reset.c
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@@ -11,6 +11,7 @@
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#include <linux/ioport.h>
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#include <linux/pm.h>
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#include <linux/export.h>
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+#include <linux/delay.h>
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#include <asm/reboot.h>
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#include <lantiq_soc.h>
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@@ -20,12 +21,45 @@
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#define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y))
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#define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x))
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-/* register definitions */
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-#define LTQ_RCU_RST 0x0010
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-#define LTQ_RCU_RST_ALL 0x40000000
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-
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-#define LTQ_RCU_RST_STAT 0x0014
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-#define LTQ_RCU_STAT_SHIFT 26
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+/* reset request register */
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+#define RCU_RST_REQ 0x0010
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+/* reset status register */
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+#define RCU_RST_STAT 0x0014
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+
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+/* reset cause */
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+#define RCU_STAT_SHIFT 26
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+/* Global SW Reset */
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+#define RCU_RD_SRST BIT(30)
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+/* Memory Controller */
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+#define RCU_RD_MC BIT(14)
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+/* PCI core */
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+#define RCU_RD_PCI BIT(13)
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+/* Voice DFE/AFE */
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+#define RCU_RD_DFE_AFE BIT(12)
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+/* DSL AFE */
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+#define RCU_RD_DSL_AFE BIT(11)
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+/* SDIO core */
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+#define RCU_RD_SDIO BIT(10)
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+/* DMA core */
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+#define RCU_RD_DMA BIT(9)
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+/* PPE core */
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+#define RCU_RD_PPE BIT(8)
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+/* ARC/DFE core */
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+#define RCU_RD_ARC_DFE BIT(7)
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+/* AHB bus */
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+#define RCU_RD_AHB BIT(6)
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+/* Ethernet MAC1 */
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+#define RCU_RD_ENET_MAC1 BIT(5)
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+/* USB and Phy core */
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+#define RCU_RD_USB BIT(4)
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+/* CPU1 subsystem */
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+#define RCU_RD_CPU1 BIT(3)
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+/* FPI bus */
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+#define RCU_RD_FPI BIT(2)
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+/* CPU0 subsystem */
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+#define RCU_RD_CPU0 BIT(1)
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+/* HW reset via HRST pin */
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+#define RCU_RD_HRST BIT(0)
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static struct resource ltq_rcu_resource =
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MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE);
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@@ -36,16 +70,23 @@ static void __iomem *ltq_rcu_membase;
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/* This function is used by the watchdog driver */
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int ltq_reset_cause(void)
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{
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- u32 val = ltq_rcu_r32(LTQ_RCU_RST_STAT);
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- return val >> LTQ_RCU_STAT_SHIFT;
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+ u32 val = ltq_rcu_r32(RCU_RST_STAT);
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+ return val >> RCU_STAT_SHIFT;
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}
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EXPORT_SYMBOL_GPL(ltq_reset_cause);
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+void ltq_reset_once(unsigned int module, ulong usec)
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+{
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
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+ udelay(usec);
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
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+}
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+
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static void ltq_machine_restart(char *command)
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{
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pr_notice("System restart\n");
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local_irq_disable();
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- ltq_rcu_w32(ltq_rcu_r32(LTQ_RCU_RST) | LTQ_RCU_RST_ALL, LTQ_RCU_RST);
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | RCU_RD_SRST, RCU_RST_REQ);
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unreachable();
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}
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--
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1.7.7.1
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