mirror of https://github.com/hak5/openwrt.git
737 lines
20 KiB
Diff
737 lines
20 KiB
Diff
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From 418e330dc60aaabdb5cf4509ec08cce07d63f32e Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 8 Mar 2012 11:18:22 +0100
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Subject: [PATCH 26/70] MIPS: lantiq: convert xway to clkdev api
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Unify xway/ase clock code and add clkdev hooks to sysctrl.c
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 13 --
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arch/mips/lantiq/xway/Makefile | 6 +-
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arch/mips/lantiq/xway/clk-ase.c | 48 ----
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arch/mips/lantiq/xway/clk-xway.c | 223 -------------------
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arch/mips/lantiq/xway/clk.c | 227 ++++++++++++++++++++
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arch/mips/lantiq/xway/sysctrl.c | 104 ++++++++-
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6 files changed, 325 insertions(+), 296 deletions(-)
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delete mode 100644 arch/mips/lantiq/xway/clk-ase.c
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delete mode 100644 arch/mips/lantiq/xway/clk-xway.c
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create mode 100644 arch/mips/lantiq/xway/clk.c
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diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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index 45e480c..e9d2dd4 100644
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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@@ -81,15 +81,6 @@
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#define LTQ_PMU_BASE_ADDR 0x1F102000
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#define LTQ_PMU_SIZE 0x1000
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-#define PMU_DMA 0x0020
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-#define PMU_EPHY 0x0080
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-#define PMU_USB 0x8041
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-#define PMU_LED 0x0800
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-#define PMU_GPT 0x1000
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-#define PMU_PPE 0x2000
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-#define PMU_FPI 0x4000
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-#define PMU_SWITCH 0x10000000
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-
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/* ETOP - ethernet */
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#define LTQ_ETOP_BASE_ADDR 0x1E180000
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#define LTQ_ETOP_SIZE 0x40000
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@@ -145,10 +136,6 @@
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extern __iomem void *ltq_ebu_membase;
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extern __iomem void *ltq_cgu_membase;
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-extern void ltq_pmu_enable(unsigned int module);
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-extern void ltq_pmu_disable(unsigned int module);
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-extern void ltq_cgu_enable(unsigned int clk);
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-
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static inline int ltq_is_ase(void)
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{
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return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE);
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diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
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index 6678402..4dcb96f 100644
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--- a/arch/mips/lantiq/xway/Makefile
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+++ b/arch/mips/lantiq/xway/Makefile
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@@ -1,7 +1,7 @@
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-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
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+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o
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-obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
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-obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
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+obj-$(CONFIG_SOC_XWAY) += prom-xway.o
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+obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o
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obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
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obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
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diff --git a/arch/mips/lantiq/xway/clk-ase.c b/arch/mips/lantiq/xway/clk-ase.c
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deleted file mode 100644
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index 6522583..0000000
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--- a/arch/mips/lantiq/xway/clk-ase.c
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+++ /dev/null
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@@ -1,48 +0,0 @@
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-/*
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License version 2 as published
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- * by the Free Software Foundation.
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- *
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- * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
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- */
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-
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-#include <linux/io.h>
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-#include <linux/export.h>
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-#include <linux/init.h>
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-#include <linux/clk.h>
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-
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-#include <asm/time.h>
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-#include <asm/irq.h>
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-#include <asm/div64.h>
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-
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-#include <lantiq_soc.h>
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-
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-/* cgu registers */
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-#define LTQ_CGU_SYS 0x0010
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-
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-unsigned int ltq_get_io_region_clock(void)
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-{
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- return CLOCK_133M;
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-}
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-EXPORT_SYMBOL(ltq_get_io_region_clock);
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-
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-unsigned int ltq_get_fpi_bus_clock(int fpi)
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-{
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- return CLOCK_133M;
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-}
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-EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
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-
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-unsigned int ltq_get_cpu_hz(void)
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-{
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- if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
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- return CLOCK_266M;
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- else
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- return CLOCK_133M;
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-}
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-EXPORT_SYMBOL(ltq_get_cpu_hz);
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-
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-unsigned int ltq_get_fpi_hz(void)
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-{
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- return CLOCK_133M;
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-}
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-EXPORT_SYMBOL(ltq_get_fpi_hz);
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diff --git a/arch/mips/lantiq/xway/clk-xway.c b/arch/mips/lantiq/xway/clk-xway.c
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deleted file mode 100644
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index 696b1a3..0000000
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--- a/arch/mips/lantiq/xway/clk-xway.c
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+++ /dev/null
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@@ -1,223 +0,0 @@
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-/*
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License version 2 as published
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- * by the Free Software Foundation.
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- *
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- * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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- */
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-
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-#include <linux/io.h>
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-#include <linux/export.h>
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-#include <linux/init.h>
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-#include <linux/clk.h>
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-
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-#include <asm/time.h>
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-#include <asm/irq.h>
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-#include <asm/div64.h>
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-
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-#include <lantiq_soc.h>
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-
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-static unsigned int ltq_ram_clocks[] = {
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- CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
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-#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
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-
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-#define BASIC_FREQUENCY_1 35328000
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-#define BASIC_FREQUENCY_2 36000000
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-#define BASIS_REQUENCY_USB 12000000
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-
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-#define GET_BITS(x, msb, lsb) \
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- (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
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-
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-#define LTQ_CGU_PLL0_CFG 0x0004
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-#define LTQ_CGU_PLL1_CFG 0x0008
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-#define LTQ_CGU_PLL2_CFG 0x000C
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-#define LTQ_CGU_SYS 0x0010
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-#define LTQ_CGU_UPDATE 0x0014
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-#define LTQ_CGU_IF_CLK 0x0018
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-#define LTQ_CGU_OSC_CON 0x001C
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-#define LTQ_CGU_SMD 0x0020
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-#define LTQ_CGU_CT1SR 0x0028
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-#define LTQ_CGU_CT2SR 0x002C
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-#define LTQ_CGU_PCMCR 0x0030
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-#define LTQ_CGU_PCI_CR 0x0034
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-#define LTQ_CGU_PD_PC 0x0038
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-#define LTQ_CGU_FMR 0x003C
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-
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-#define CGU_PLL0_PHASE_DIVIDER_ENABLE \
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- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
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-#define CGU_PLL0_BYPASS \
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- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
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-#define CGU_PLL0_CFG_DSMSEL \
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- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
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-#define CGU_PLL0_CFG_FRAC_EN \
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- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
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-#define CGU_PLL1_SRC \
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- (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
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-#define CGU_PLL2_PHASE_DIVIDER_ENABLE \
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- (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
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-#define CGU_SYS_FPI_SEL (1 << 6)
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-#define CGU_SYS_DDR_SEL 0x3
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-#define CGU_PLL0_SRC (1 << 29)
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-
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-#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
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-#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
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-#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
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-#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
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-#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
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-
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-static unsigned int ltq_get_pll0_fdiv(void);
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-
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-static inline unsigned int get_input_clock(int pll)
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-{
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- switch (pll) {
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- case 0:
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- if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
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- return BASIS_REQUENCY_USB;
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- else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
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- return BASIC_FREQUENCY_1;
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- else
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- return BASIC_FREQUENCY_2;
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- case 1:
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- if (CGU_PLL1_SRC)
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- return BASIS_REQUENCY_USB;
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- else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
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- return BASIC_FREQUENCY_1;
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- else
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- return BASIC_FREQUENCY_2;
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- case 2:
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- switch (CGU_PLL2_SRC) {
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- case 0:
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- return ltq_get_pll0_fdiv();
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- case 1:
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- return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
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- BASIC_FREQUENCY_1 :
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- BASIC_FREQUENCY_2;
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- case 2:
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- return BASIS_REQUENCY_USB;
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- }
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- default:
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- return 0;
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- }
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-}
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-
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-static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
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-{
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- u64 res, clock = get_input_clock(pll);
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-
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- res = num * clock;
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- do_div(res, den);
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- return res;
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-}
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-
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-static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
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- unsigned int K)
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-{
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- unsigned int num = ((N + 1) << 10) + K;
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- unsigned int den = (M + 1) << 10;
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-
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- return cal_dsm(pll, num, den);
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-}
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-
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-static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
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- unsigned int K)
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-{
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- unsigned int num = ((N + 1) << 11) + K + 512;
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- unsigned int den = (M + 1) << 11;
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-
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- return cal_dsm(pll, num, den);
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-}
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-
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-static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
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- unsigned int K)
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-{
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- unsigned int num = K >= 512 ?
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- ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
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- unsigned int den = (M + 1) << 12;
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-
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- return cal_dsm(pll, num, den);
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-}
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-
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-static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
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- unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
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-{
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- if (!dsmsel)
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- return mash_dsm(pll, M, N, K);
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- else if (!phase_div_en)
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- return mash_dsm(pll, M, N, K);
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- else
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- return ssff_dsm_2(pll, M, N, K);
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-}
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-
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-static inline unsigned int ltq_get_pll0_fosc(void)
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-{
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- if (CGU_PLL0_BYPASS)
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- return get_input_clock(0);
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- else
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- return !CGU_PLL0_CFG_FRAC_EN
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- ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0,
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- CGU_PLL0_CFG_DSMSEL,
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- CGU_PLL0_PHASE_DIVIDER_ENABLE)
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- : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN,
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- CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL,
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- CGU_PLL0_PHASE_DIVIDER_ENABLE);
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-}
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-
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-static unsigned int ltq_get_pll0_fdiv(void)
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-{
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- unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
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-
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- return (ltq_get_pll0_fosc() + (div >> 1)) / div;
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-}
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-
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-unsigned int ltq_get_io_region_clock(void)
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-{
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- unsigned int ret = ltq_get_pll0_fosc();
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-
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- switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
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- default:
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- case 0:
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- return (ret + 1) / 2;
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- case 1:
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- return (ret * 2 + 2) / 5;
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- case 2:
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- return (ret + 1) / 3;
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- case 3:
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- return (ret + 2) / 4;
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- }
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-}
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-EXPORT_SYMBOL(ltq_get_io_region_clock);
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-
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-unsigned int ltq_get_fpi_bus_clock(int fpi)
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-{
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- unsigned int ret = ltq_get_io_region_clock();
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-
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- if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL))
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- ret >>= 1;
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- return ret;
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-}
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-EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
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-
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-unsigned int ltq_get_cpu_hz(void)
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-{
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- switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
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- case 0:
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- return CLOCK_333M;
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- case 4:
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- return DDR_HZ;
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- case 8:
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- return DDR_HZ << 1;
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- default:
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- return DDR_HZ >> 1;
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- }
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-}
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-EXPORT_SYMBOL(ltq_get_cpu_hz);
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-
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-unsigned int ltq_get_fpi_hz(void)
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-{
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- unsigned int ddr_clock = DDR_HZ;
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-
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- if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
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- return ddr_clock >> 1;
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- return ddr_clock;
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-}
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-EXPORT_SYMBOL(ltq_get_fpi_hz);
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diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
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new file mode 100644
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index 0000000..f3b50fc
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--- /dev/null
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+++ b/arch/mips/lantiq/xway/clk.c
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@@ -0,0 +1,227 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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||
|
+ * under the terms of the GNU General Public License version 2 as published
|
||
|
+ * by the Free Software Foundation.
|
||
|
+ *
|
||
|
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
|
||
|
+ */
|
||
|
+
|
||
|
+#include <linux/io.h>
|
||
|
+#include <linux/export.h>
|
||
|
+#include <linux/init.h>
|
||
|
+#include <linux/clk.h>
|
||
|
+
|
||
|
+#include <asm/time.h>
|
||
|
+#include <asm/irq.h>
|
||
|
+#include <asm/div64.h>
|
||
|
+
|
||
|
+#include <lantiq_soc.h>
|
||
|
+
|
||
|
+#include "../clk.h"
|
||
|
+
|
||
|
+static unsigned int ltq_ram_clocks[] = {
|
||
|
+ CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
|
||
|
+#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
|
||
|
+
|
||
|
+#define BASIC_FREQUENCY_1 35328000
|
||
|
+#define BASIC_FREQUENCY_2 36000000
|
||
|
+#define BASIS_REQUENCY_USB 12000000
|
||
|
+
|
||
|
+#define GET_BITS(x, msb, lsb) \
|
||
|
+ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
|
||
|
+
|
||
|
+/* legacy xway clock */
|
||
|
+#define LTQ_CGU_PLL0_CFG 0x0004
|
||
|
+#define LTQ_CGU_PLL1_CFG 0x0008
|
||
|
+#define LTQ_CGU_PLL2_CFG 0x000C
|
||
|
+#define LTQ_CGU_SYS 0x0010
|
||
|
+#define LTQ_CGU_UPDATE 0x0014
|
||
|
+#define LTQ_CGU_IF_CLK 0x0018
|
||
|
+#define LTQ_CGU_OSC_CON 0x001C
|
||
|
+#define LTQ_CGU_SMD 0x0020
|
||
|
+#define LTQ_CGU_CT1SR 0x0028
|
||
|
+#define LTQ_CGU_CT2SR 0x002C
|
||
|
+#define LTQ_CGU_PCMCR 0x0030
|
||
|
+#define LTQ_CGU_PCI_CR 0x0034
|
||
|
+#define LTQ_CGU_PD_PC 0x0038
|
||
|
+#define LTQ_CGU_FMR 0x003C
|
||
|
+
|
||
|
+#define CGU_PLL0_PHASE_DIVIDER_ENABLE \
|
||
|
+ (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
|
||
|
+#define CGU_PLL0_BYPASS \
|
||
|
+ (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
|
||
|
+#define CGU_PLL0_CFG_DSMSEL \
|
||
|
+ (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
|
||
|
+#define CGU_PLL0_CFG_FRAC_EN \
|
||
|
+ (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
|
||
|
+#define CGU_PLL1_SRC \
|
||
|
+ (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
|
||
|
+#define CGU_PLL2_PHASE_DIVIDER_ENABLE \
|
||
|
+ (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
|
||
|
+#define CGU_SYS_FPI_SEL (1 << 6)
|
||
|
+#define CGU_SYS_DDR_SEL 0x3
|
||
|
+#define CGU_PLL0_SRC (1 << 29)
|
||
|
+
|
||
|
+#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
|
||
|
+#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
|
||
|
+#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
|
||
|
+#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
|
||
|
+#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
|
||
|
+
|
||
|
+/* vr9 clock */
|
||
|
+#define LTQ_CGU_SYS_VR9 0x0c
|
||
|
+#define LTQ_CGU_IF_CLK_VR9 0x24
|
||
|
+
|
||
|
+
|
||
|
+static unsigned int ltq_get_pll0_fdiv(void);
|
||
|
+
|
||
|
+static inline unsigned int get_input_clock(int pll)
|
||
|
+{
|
||
|
+ switch (pll) {
|
||
|
+ case 0:
|
||
|
+ if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
|
||
|
+ return BASIS_REQUENCY_USB;
|
||
|
+ else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
|
||
|
+ return BASIC_FREQUENCY_1;
|
||
|
+ else
|
||
|
+ return BASIC_FREQUENCY_2;
|
||
|
+ case 1:
|
||
|
+ if (CGU_PLL1_SRC)
|
||
|
+ return BASIS_REQUENCY_USB;
|
||
|
+ else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
|
||
|
+ return BASIC_FREQUENCY_1;
|
||
|
+ else
|
||
|
+ return BASIC_FREQUENCY_2;
|
||
|
+ case 2:
|
||
|
+ switch (CGU_PLL2_SRC) {
|
||
|
+ case 0:
|
||
|
+ return ltq_get_pll0_fdiv();
|
||
|
+ case 1:
|
||
|
+ return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
|
||
|
+ BASIC_FREQUENCY_1 :
|
||
|
+ BASIC_FREQUENCY_2;
|
||
|
+ case 2:
|
||
|
+ return BASIS_REQUENCY_USB;
|
||
|
+ }
|
||
|
+ default:
|
||
|
+ return 0;
|
||
|
+ }
|
||
|
+}
|
||
|
+
|
||
|
+static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
|
||
|
+{
|
||
|
+ u64 res, clock = get_input_clock(pll);
|
||
|
+
|
||
|
+ res = num * clock;
|
||
|
+ do_div(res, den);
|
||
|
+ return res;
|
||
|
+}
|
||
|
+
|
||
|
+static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
|
||
|
+ unsigned int K)
|
||
|
+{
|
||
|
+ unsigned int num = ((N + 1) << 10) + K;
|
||
|
+ unsigned int den = (M + 1) << 10;
|
||
|
+
|
||
|
+ return cal_dsm(pll, num, den);
|
||
|
+}
|
||
|
+
|
||
|
+static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
|
||
|
+ unsigned int K)
|
||
|
+{
|
||
|
+ unsigned int num = ((N + 1) << 11) + K + 512;
|
||
|
+ unsigned int den = (M + 1) << 11;
|
||
|
+
|
||
|
+ return cal_dsm(pll, num, den);
|
||
|
+}
|
||
|
+
|
||
|
+static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
|
||
|
+ unsigned int K)
|
||
|
+{
|
||
|
+ unsigned int num = K >= 512 ?
|
||
|
+ ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
|
||
|
+ unsigned int den = (M + 1) << 12;
|
||
|
+
|
||
|
+ return cal_dsm(pll, num, den);
|
||
|
+}
|
||
|
+
|
||
|
+static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
|
||
|
+ unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
|
||
|
+{
|
||
|
+ if (!dsmsel)
|
||
|
+ return mash_dsm(pll, M, N, K);
|
||
|
+ else if (!phase_div_en)
|
||
|
+ return mash_dsm(pll, M, N, K);
|
||
|
+ else
|
||
|
+ return ssff_dsm_2(pll, M, N, K);
|
||
|
+}
|
||
|
+
|
||
|
+static inline unsigned int ltq_get_pll0_fosc(void)
|
||
|
+{
|
||
|
+ if (CGU_PLL0_BYPASS)
|
||
|
+ return get_input_clock(0);
|
||
|
+ else
|
||
|
+ return !CGU_PLL0_CFG_FRAC_EN
|
||
|
+ ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0,
|
||
|
+ CGU_PLL0_CFG_DSMSEL,
|
||
|
+ CGU_PLL0_PHASE_DIVIDER_ENABLE)
|
||
|
+ : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN,
|
||
|
+ CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL,
|
||
|
+ CGU_PLL0_PHASE_DIVIDER_ENABLE);
|
||
|
+}
|
||
|
+
|
||
|
+static unsigned int ltq_get_pll0_fdiv(void)
|
||
|
+{
|
||
|
+ unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
|
||
|
+
|
||
|
+ return (ltq_get_pll0_fosc() + (div >> 1)) / div;
|
||
|
+}
|
||
|
+
|
||
|
+unsigned long ltq_danube_io_region_clock(void)
|
||
|
+{
|
||
|
+ unsigned int ret = ltq_get_pll0_fosc();
|
||
|
+
|
||
|
+ switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
|
||
|
+ default:
|
||
|
+ case 0:
|
||
|
+ return (ret + 1) / 2;
|
||
|
+ case 1:
|
||
|
+ return (ret * 2 + 2) / 5;
|
||
|
+ case 2:
|
||
|
+ return (ret + 1) / 3;
|
||
|
+ case 3:
|
||
|
+ return (ret + 2) / 4;
|
||
|
+ }
|
||
|
+}
|
||
|
+
|
||
|
+unsigned long ltq_danube_fpi_bus_clock(int fpi)
|
||
|
+{
|
||
|
+ unsigned long ret = ltq_danube_io_region_clock();
|
||
|
+
|
||
|
+ if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL))
|
||
|
+ ret >>= 1;
|
||
|
+ return ret;
|
||
|
+}
|
||
|
+
|
||
|
+unsigned long ltq_danube_cpu_hz(void)
|
||
|
+{
|
||
|
+ switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
|
||
|
+ case 0:
|
||
|
+ return CLOCK_333M;
|
||
|
+ case 4:
|
||
|
+ return DDR_HZ;
|
||
|
+ case 8:
|
||
|
+ return DDR_HZ << 1;
|
||
|
+ default:
|
||
|
+ return DDR_HZ >> 1;
|
||
|
+ }
|
||
|
+}
|
||
|
+
|
||
|
+unsigned long ltq_danube_fpi_hz(void)
|
||
|
+{
|
||
|
+ unsigned long ddr_clock = DDR_HZ;
|
||
|
+
|
||
|
+ if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
|
||
|
+ return ddr_clock >> 1;
|
||
|
+ return ddr_clock;
|
||
|
+}
|
||
|
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
|
||
|
index 8fd13a1..c5782b5 100644
|
||
|
--- a/arch/mips/lantiq/xway/sysctrl.c
|
||
|
+++ b/arch/mips/lantiq/xway/sysctrl.c
|
||
|
@@ -8,17 +8,48 @@
|
||
|
|
||
|
#include <linux/ioport.h>
|
||
|
#include <linux/export.h>
|
||
|
+#include <linux/clkdev.h>
|
||
|
|
||
|
#include <lantiq_soc.h>
|
||
|
|
||
|
+#include "../clk.h"
|
||
|
#include "../devices.h"
|
||
|
|
||
|
/* clock control register */
|
||
|
#define LTQ_CGU_IFCCR 0x0018
|
||
|
+/* system clock register */
|
||
|
+#define LTQ_CGU_SYS 0x0010
|
||
|
|
||
|
/* the enable / disable registers */
|
||
|
#define LTQ_PMU_PWDCR 0x1C
|
||
|
#define LTQ_PMU_PWDSR 0x20
|
||
|
+#define LTQ_PMU_PWDCR1 0x24
|
||
|
+#define LTQ_PMU_PWDSR1 0x28
|
||
|
+
|
||
|
+#define PWDCR(x) ((x) ? (LTQ_PMU_PWDCR1) : (LTQ_PMU_PWDCR))
|
||
|
+#define PWDSR(x) ((x) ? (LTQ_PMU_PWDSR1) : (LTQ_PMU_PWDSR))
|
||
|
+
|
||
|
+/* CGU - clock generation unit */
|
||
|
+#define CGU_EPHY 0x10
|
||
|
+
|
||
|
+/* PMU - power management unit */
|
||
|
+#define PMU_DMA 0x0020
|
||
|
+#define PMU_SPI 0x0100
|
||
|
+#define PMU_EPHY 0x0080
|
||
|
+#define PMU_USB 0x8041
|
||
|
+#define PMU_STP 0x0800
|
||
|
+#define PMU_GPT 0x1000
|
||
|
+#define PMU_PPE 0x2000
|
||
|
+#define PMU_FPI 0x4000
|
||
|
+#define PMU_SWITCH 0x10000000
|
||
|
+#define PMU_AHBS 0x2000
|
||
|
+#define PMU_AHBM 0x8000
|
||
|
+#define PMU_PCIE_CLK 0x80000000
|
||
|
+
|
||
|
+#define PMU1_PCIE_PHY 0x0001
|
||
|
+#define PMU1_PCIE_CTL 0x0002
|
||
|
+#define PMU1_PCIE_MSI 0x0020
|
||
|
+#define PMU1_PCIE_PDI 0x0010
|
||
|
|
||
|
#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y))
|
||
|
#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x))
|
||
|
@@ -36,28 +67,64 @@ void __iomem *ltq_cgu_membase;
|
||
|
void __iomem *ltq_ebu_membase;
|
||
|
static void __iomem *ltq_pmu_membase;
|
||
|
|
||
|
-void ltq_cgu_enable(unsigned int clk)
|
||
|
+static int ltq_cgu_enable(struct clk *clk)
|
||
|
{
|
||
|
- ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR);
|
||
|
+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk->bits, LTQ_CGU_IFCCR);
|
||
|
+ return 0;
|
||
|
}
|
||
|
|
||
|
-void ltq_pmu_enable(unsigned int module)
|
||
|
+static void ltq_cgu_disable(struct clk *clk)
|
||
|
+{
|
||
|
+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~clk->bits, LTQ_CGU_IFCCR);
|
||
|
+}
|
||
|
+
|
||
|
+static int ltq_pmu_enable(struct clk *clk)
|
||
|
{
|
||
|
int err = 1000000;
|
||
|
|
||
|
- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
|
||
|
- do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
|
||
|
+ ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) & ~clk->bits,
|
||
|
+ PWDCR(clk->module));
|
||
|
+ do {} while (--err && (ltq_pmu_r32(PWDSR(clk->module)) & clk->bits));
|
||
|
|
||
|
if (!err)
|
||
|
panic("activating PMU module failed!\n");
|
||
|
+
|
||
|
+ return 0;
|
||
|
}
|
||
|
-EXPORT_SYMBOL(ltq_pmu_enable);
|
||
|
|
||
|
-void ltq_pmu_disable(unsigned int module)
|
||
|
+static void ltq_pmu_disable(struct clk *clk)
|
||
|
{
|
||
|
- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
|
||
|
+ ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | clk->bits, LTQ_PMU_PWDCR);
|
||
|
+}
|
||
|
+
|
||
|
+static inline void clkdev_add_pmu(const char *dev, const char *con,
|
||
|
+ unsigned int module, unsigned int bits)
|
||
|
+{
|
||
|
+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
|
||
|
+
|
||
|
+ clk->cl.dev_id = dev;
|
||
|
+ clk->cl.con_id = con;
|
||
|
+ clk->cl.clk = clk;
|
||
|
+ clk->enable = ltq_pmu_enable;
|
||
|
+ clk->disable = ltq_pmu_disable;
|
||
|
+ clk->module = module;
|
||
|
+ clk->bits = bits;
|
||
|
+ clkdev_add(&clk->cl);
|
||
|
+}
|
||
|
+
|
||
|
+static inline void clkdev_add_cgu(const char *dev, const char *con,
|
||
|
+ unsigned int bits)
|
||
|
+{
|
||
|
+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
|
||
|
+
|
||
|
+ clk->cl.dev_id = dev;
|
||
|
+ clk->cl.con_id = con;
|
||
|
+ clk->cl.clk = clk;
|
||
|
+ clk->enable = ltq_cgu_enable;
|
||
|
+ clk->disable = ltq_cgu_disable;
|
||
|
+ clk->bits = bits;
|
||
|
+ clkdev_add(&clk->cl);
|
||
|
}
|
||
|
-EXPORT_SYMBOL(ltq_pmu_disable);
|
||
|
|
||
|
void __init ltq_soc_init(void)
|
||
|
{
|
||
|
@@ -75,4 +142,23 @@ void __init ltq_soc_init(void)
|
||
|
|
||
|
/* make sure to unprotect the memory region where flash is located */
|
||
|
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
|
||
|
+
|
||
|
+ /* add our clocks */
|
||
|
+ clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
|
||
|
+ clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
|
||
|
+ clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
|
||
|
+ clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
|
||
|
+ if (ltq_is_ase()) {
|
||
|
+ if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
|
||
|
+ clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
|
||
|
+ else
|
||
|
+ clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
|
||
|
+ clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY),
|
||
|
+ clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
|
||
|
+ } else {
|
||
|
+ clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
|
||
|
+ ltq_danube_io_region_clock());
|
||
|
+ if (ltq_is_ar9())
|
||
|
+ clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
|
||
|
+ }
|
||
|
}
|
||
|
--
|
||
|
1.7.7.1
|
||
|
|