mirror of https://github.com/hak5/openwrt.git
47 lines
1.5 KiB
Diff
47 lines
1.5 KiB
Diff
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From a0a4f406c7e90b2be66e88ea8b21699940c0823f Mon Sep 17 00:00:00 2001
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From: Joao Pinto <Joao.Pinto@synopsys.com>
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Date: Thu, 10 Mar 2016 14:44:44 -0600
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Subject: [PATCH 57/70] PCI: designware: Add default link up check if
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sub-driver doesn't override
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Add a default DesignWare "link_up" test for use when a sub-driver doesn't
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supply its own pcie_host_ops.link_up() method.
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[bhelgaas: changelog, split into its own patch]
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Signed-off-by: Joao Pinto <jpinto@synopsys.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
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---
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drivers/pci/host/pcie-designware.c | 10 +++++++++-
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1 file changed, 9 insertions(+), 1 deletion(-)
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--- a/drivers/pci/host/pcie-designware.c
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+++ b/drivers/pci/host/pcie-designware.c
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@@ -70,6 +70,11 @@
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define PCIE_ATU_UPPER_TARGET 0x91C
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+/* PCIe Port Logic registers */
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+#define PLR_OFFSET 0x700
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+#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
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+#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
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+
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static struct pci_ops dw_pcie_ops;
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int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
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@@ -401,10 +406,13 @@ int dw_pcie_wait_for_link(struct pcie_po
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int dw_pcie_link_up(struct pcie_port *pp)
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{
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+ u32 val;
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+
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if (pp->ops->link_up)
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return pp->ops->link_up(pp);
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- return 0;
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+ val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
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+ return val & PCIE_PHY_DEBUG_R1_LINK_UP;
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}
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static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
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