mirror of https://github.com/hak5/openwrt.git
239 lines
7.7 KiB
C
239 lines
7.7 KiB
C
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/*
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* Gary Jennejohn (C) 2003 <gj@denx.de>
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* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Routines for generic manipulation of the interrupts found on the
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* AMAZON boards.
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <asm/amazon/amazon.h>
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#include <asm/amazon/irq.h>
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#include <asm/bootinfo.h>
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#include <asm/irq_cpu.h>
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#include <asm/irq.h>
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#include <asm/time.h>
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static void amazon_disable_irq(unsigned int irq_nr)
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{
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/* have to access the correct register here */
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if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
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/* access IM0 DMA channels */
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*AMAZON_ICU_IM0_IER &= (~(AMAZON_DMA_H_MASK));
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else if (irq_nr <= INT_NUM_IM0_IRL31 && irq_nr >= INT_NUM_IM0_IRL12)
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/* access IM0 except DMA*/
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*AMAZON_ICU_IM0_IER &= (~AMAZON_ICU_IM0_IER_IR(irq_nr));
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else if (irq_nr <= INT_NUM_IM1_IRL31 && irq_nr >= INT_NUM_IM1_IRL0)
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/* access IM1 */
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*AMAZON_ICU_IM1_IER &= (~AMAZON_ICU_IM1_IER_IR(irq_nr - INT_NUM_IM1_IRL0));
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else if (irq_nr <= INT_NUM_IM2_IRL31 && irq_nr >= INT_NUM_IM2_IRL0)
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/* access IM2 */
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*AMAZON_ICU_IM2_IER &= (~AMAZON_ICU_IM2_IER_IR(irq_nr - INT_NUM_IM2_IRL0));
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else if (irq_nr <= INT_NUM_IM3_IRL31 && irq_nr >= INT_NUM_IM3_IRL0)
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/* access IM3 */
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*AMAZON_ICU_IM3_IER &= (~AMAZON_ICU_IM3_IER_IR((irq_nr - INT_NUM_IM3_IRL0)));
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else if (irq_nr <= INT_NUM_IM4_IRL31 && irq_nr >= INT_NUM_IM4_IRL0)
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/* access IM4 */
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*AMAZON_ICU_IM4_IER &= (~AMAZON_ICU_IM4_IER_IR((irq_nr - INT_NUM_IM4_IRL0)));
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}
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static void amazon_mask_and_ack_irq(unsigned int irq_nr)
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{
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/* have to access the correct register here */
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if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0) {
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/* access IM0 DMA channels */
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*AMAZON_ICU_IM0_IER &= (~(AMAZON_DMA_H_MASK)); /* mask */
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*AMAZON_ICU_IM0_ISR = AMAZON_DMA_H_MASK; /* ack */
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} else if (irq_nr <= INT_NUM_IM0_IRL31 && irq_nr >= INT_NUM_IM0_IRL12) {
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/* access IM0 except DMA */
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*AMAZON_ICU_IM0_IER &= ~AMAZON_ICU_IM0_IER_IR(irq_nr - INT_NUM_IM0_IRL0); /* mask */
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*AMAZON_ICU_IM0_ISR = AMAZON_ICU_IM0_ISR_IR(irq_nr - INT_NUM_IM0_IRL0); /* ack */
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} else if (irq_nr <= INT_NUM_IM1_IRL31 && irq_nr >= INT_NUM_IM1_IRL0) {
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/* access IM1 */
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*AMAZON_ICU_IM1_IER &= ~AMAZON_ICU_IM1_IER_IR(irq_nr - INT_NUM_IM1_IRL0); /* mask */
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*AMAZON_ICU_IM1_ISR = AMAZON_ICU_IM1_ISR_IR(irq_nr - INT_NUM_IM1_IRL0); /* ack */
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} else if (irq_nr <= INT_NUM_IM2_IRL31 && irq_nr >= INT_NUM_IM2_IRL0) {
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/* access IM2 */
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*AMAZON_ICU_IM2_IER &= ~AMAZON_ICU_IM2_IER_IR(irq_nr - INT_NUM_IM2_IRL0); /* mask */
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*AMAZON_ICU_IM2_ISR = AMAZON_ICU_IM2_ISR_IR(irq_nr - INT_NUM_IM2_IRL0); /* ack */
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} else if (irq_nr <= INT_NUM_IM3_IRL31 && irq_nr >= INT_NUM_IM3_IRL0) {
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/* access IM3 */
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*AMAZON_ICU_IM3_IER &= ~AMAZON_ICU_IM3_IER_IR(irq_nr - INT_NUM_IM3_IRL0); /* mask */
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*AMAZON_ICU_IM3_ISR = AMAZON_ICU_IM3_ISR_IR(irq_nr - INT_NUM_IM3_IRL0); /* ack */
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} else if (irq_nr <= INT_NUM_IM4_IRL31 && irq_nr >= INT_NUM_IM4_IRL0) {
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*AMAZON_ICU_IM4_IER &= ~AMAZON_ICU_IM4_IER_IR(irq_nr - INT_NUM_IM4_IRL0); /* mask */
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*AMAZON_ICU_IM4_ISR = AMAZON_ICU_IM4_ISR_IR(irq_nr - INT_NUM_IM4_IRL0); /* ack */
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}
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}
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static void amazon_enable_irq(unsigned int irq_nr)
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{
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/* have to access the correct register here */
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if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
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/* access IM0 DMA*/
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*AMAZON_ICU_IM0_IER |= AMAZON_DMA_H_MASK;
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else if (irq_nr <= INT_NUM_IM0_IRL31 && irq_nr >= INT_NUM_IM0_IRL12)
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/* access IM0 except DMA*/
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*AMAZON_ICU_IM0_IER |= AMAZON_ICU_IM0_IER_IR(irq_nr - INT_NUM_IM0_IRL0);
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else if (irq_nr <= INT_NUM_IM1_IRL31 && irq_nr >= INT_NUM_IM1_IRL0)
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/* access IM1 */
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*AMAZON_ICU_IM1_IER |= AMAZON_ICU_IM1_IER_IR(irq_nr - INT_NUM_IM1_IRL0);
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else if (irq_nr <= INT_NUM_IM2_IRL31 && irq_nr >= INT_NUM_IM2_IRL0)
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/* access IM2 */
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*AMAZON_ICU_IM2_IER |= AMAZON_ICU_IM2_IER_IR(irq_nr - INT_NUM_IM2_IRL0);
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else if (irq_nr <= INT_NUM_IM3_IRL31 && irq_nr >= INT_NUM_IM3_IRL0)
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/* access IM3 */
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*AMAZON_ICU_IM3_IER |= AMAZON_ICU_IM3_IER_IR((irq_nr - INT_NUM_IM3_IRL0));
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else if (irq_nr <= INT_NUM_IM4_IRL31 && irq_nr >= INT_NUM_IM4_IRL0)
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/* access IM4 */
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*AMAZON_ICU_IM4_IER |= AMAZON_ICU_IM4_IER_IR((irq_nr - INT_NUM_IM4_IRL0));
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}
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static unsigned int amazon_startup_irq(unsigned int irq)
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{
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amazon_enable_irq(irq);
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return 0;
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}
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static void amazon_end_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
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amazon_enable_irq(irq);
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}
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}
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static struct hw_interrupt_type amazon_irq_type = {
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"AMAZON",
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.startup = amazon_startup_irq,
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.enable = amazon_enable_irq,
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.disable = amazon_disable_irq,
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.unmask = amazon_enable_irq,
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.ack = amazon_mask_and_ack_irq,
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.mask = amazon_disable_irq,
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.mask_ack = amazon_mask_and_ack_irq,
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.end = amazon_end_irq
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};
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/* Cascaded interrupts from IM0 */
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static inline void amazon_hw0_irqdispatch(void)
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{
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u32 irq;
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irq = (*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM0_VEC_MASK;
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if (irq <= 11 && irq >= 0) {
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//DMA fixed to IM0_IRL0
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irq = 0;
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}
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do_IRQ(irq + INT_NUM_IM0_IRL0);
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}
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/* Cascaded interrupts from IM1 */
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static inline void amazon_hw1_irqdispatch(void)
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{
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u32 irq;
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irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM1_VEC_MASK) >> 5;
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do_IRQ(irq + INT_NUM_IM1_IRL0);
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}
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/* Cascaded interrupts from IM2 */
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static inline void amazon_hw2_irqdispatch(void)
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{
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u32 irq;
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irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM2_VEC_MASK) >> 10;
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do_IRQ(irq + INT_NUM_IM2_IRL0);
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}
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/* Cascaded interrupts from IM3 */
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static inline void amazon_hw3_irqdispatch(void)
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{
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u32 irq;
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irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM3_VEC_MASK) >> 15;
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do_IRQ(irq + INT_NUM_IM3_IRL0);
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}
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/* Cascaded interrupts from IM4 */
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static inline void amazon_hw4_irqdispatch(void)
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{
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u32 irq;
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irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM4_VEC_MASK) >> 20;
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do_IRQ(irq + INT_NUM_IM4_IRL0);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & CAUSEF_IP7){
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do_IRQ(MIPS_CPU_TIMER_IRQ);
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}
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else if (pending & CAUSEF_IP2)
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amazon_hw0_irqdispatch();
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else if (pending & CAUSEF_IP3)
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amazon_hw1_irqdispatch();
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else if (pending & CAUSEF_IP4)
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amazon_hw2_irqdispatch();
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else if (pending & CAUSEF_IP5)
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amazon_hw3_irqdispatch();
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else if (pending & CAUSEF_IP6)
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amazon_hw4_irqdispatch();
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else
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printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
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}
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static struct irqaction cascade = {
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.handler = no_action,
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.flags = SA_INTERRUPT,
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.name = "cascade",
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};
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/* Function for careful CP0 interrupt mask access */
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void __init arch_init_irq(void)
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{
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int i;
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/* mask all interrupt sources */
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*AMAZON_ICU_IM0_IER = 0;
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*AMAZON_ICU_IM1_IER = 0;
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*AMAZON_ICU_IM2_IER = 0;
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*AMAZON_ICU_IM3_IER = 0;
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*AMAZON_ICU_IM4_IER = 0;
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mips_cpu_irq_init();
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/* set up irq cascade */
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for (i = 2; i <= 6; i++) {
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setup_irq(i, &cascade);
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}
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for (i = INT_NUM_IRQ0; i <= INT_NUM_IM4_IRL31; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 1;
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set_irq_chip(i, &amazon_irq_type);
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}
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}
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