mirror of https://github.com/hak5/openwrt.git
224 lines
7.5 KiB
Diff
224 lines
7.5 KiB
Diff
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Wrap some long lines.
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Prefer seq_puts() over seq_printf().
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space to tab conversions.
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Spelling error fix.
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Signed-off-by: Andrew Lunn <andrew@lunn.ch>
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---
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drivers/gpio/gpio-mvebu.c | 77 ++++++++++++++++++++++++++---------------------
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1 file changed, 42 insertions(+), 35 deletions(-)
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--- a/drivers/gpio/gpio-mvebu.c
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+++ b/drivers/gpio/gpio-mvebu.c
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@@ -59,7 +59,7 @@
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#define GPIO_LEVEL_MASK_OFF 0x001c
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/* The MV78200 has per-CPU registers for edge mask and level mask */
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-#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
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+#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
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#define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
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/* The Armada XP has per-CPU registers for interrupt cause, interrupt
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@@ -69,11 +69,11 @@
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#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
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#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
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-#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
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-#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
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+#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
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+#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
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#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
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-#define MVEBU_MAX_GPIO_PER_BANK 32
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+#define MVEBU_MAX_GPIO_PER_BANK 32
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struct mvebu_gpio_chip {
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struct gpio_chip chip;
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@@ -82,9 +82,9 @@ struct mvebu_gpio_chip {
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void __iomem *percpu_membase;
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int irqbase;
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struct irq_domain *domain;
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- int soc_variant;
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+ int soc_variant;
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- /* Used to preserve GPIO registers accross suspend/resume */
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+ /* Used to preserve GPIO registers across suspend/resume */
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u32 out_reg;
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u32 io_conf_reg;
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u32 blink_en_reg;
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@@ -107,7 +107,8 @@ static inline void __iomem *mvebu_gpiore
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return mvchip->membase + GPIO_BLINK_EN_OFF;
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}
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-static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
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+static inline void __iomem *
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+mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_IO_CONF_OFF;
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}
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@@ -117,12 +118,14 @@ static inline void __iomem *mvebu_gpiore
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return mvchip->membase + GPIO_IN_POL_OFF;
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}
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-static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
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+static inline void __iomem *
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+mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_DATA_IN_OFF;
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}
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-static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
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+static inline void __iomem *
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+mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
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{
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int cpu;
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@@ -132,13 +135,15 @@ static inline void __iomem *mvebu_gpiore
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return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
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case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
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cpu = smp_processor_id();
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- return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
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+ return mvchip->percpu_membase +
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+ GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
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default:
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BUG();
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}
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}
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-static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
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+static inline void __iomem *
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+mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
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{
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int cpu;
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@@ -150,7 +155,8 @@ static inline void __iomem *mvebu_gpiore
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return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
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case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
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cpu = smp_processor_id();
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- return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
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+ return mvchip->percpu_membase +
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+ GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
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default:
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BUG();
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}
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@@ -168,7 +174,8 @@ static void __iomem *mvebu_gpioreg_level
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return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
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case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
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cpu = smp_processor_id();
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- return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
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+ return mvchip->percpu_membase +
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+ GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
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default:
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BUG();
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}
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@@ -364,22 +371,22 @@ static void mvebu_gpio_level_irq_unmask(
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* value of the line or the opposite value.
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*
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* Level IRQ handlers: DATA_IN is used directly as cause register.
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- * Interrupt are masked by LEVEL_MASK registers.
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+ * Interrupt are masked by LEVEL_MASK registers.
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* Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
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- * Interrupt are masked by EDGE_MASK registers.
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+ * Interrupt are masked by EDGE_MASK registers.
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* Both-edge handlers: Similar to regular Edge handlers, but also swaps
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- * the polarity to catch the next line transaction.
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- * This is a race condition that might not perfectly
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- * work on some use cases.
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+ * the polarity to catch the next line transaction.
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+ * This is a race condition that might not perfectly
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+ * work on some use cases.
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*
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* Every eight GPIO lines are grouped (OR'ed) before going up to main
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* cause register.
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*
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- * EDGE cause mask
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- * data-in /--------| |-----| |----\
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- * -----| |----- ---- to main cause reg
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- * X \----------------| |----/
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- * polarity LEVEL mask
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+ * EDGE cause mask
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+ * data-in /--------| |-----| |----\
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+ * -----| |----- ---- to main cause reg
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+ * X \----------------| |----/
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+ * polarity LEVEL mask
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*
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****************************************************************************/
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@@ -394,9 +401,8 @@ static int mvebu_gpio_irq_set_type(struc
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pin = d->hwirq;
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u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
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- if (!u) {
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+ if (!u)
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return -EINVAL;
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- }
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type &= IRQ_TYPE_SENSE_MASK;
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if (type == IRQ_TYPE_NONE)
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@@ -529,13 +535,13 @@ static void mvebu_gpio_dbg_show(struct s
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(data_in ^ in_pol) & msk ? "hi" : "lo",
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in_pol & msk ? "lo" : "hi");
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if (!((edg_msk | lvl_msk) & msk)) {
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- seq_printf(s, " disabled\n");
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+ seq_puts(s, " disabled\n");
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continue;
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}
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if (edg_msk & msk)
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- seq_printf(s, " edge ");
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+ seq_puts(s, " edge ");
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if (lvl_msk & msk)
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- seq_printf(s, " level");
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+ seq_puts(s, " level");
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seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
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}
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}
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@@ -546,15 +552,15 @@ static void mvebu_gpio_dbg_show(struct s
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static const struct of_device_id mvebu_gpio_of_match[] = {
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{
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.compatible = "marvell,orion-gpio",
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- .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
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+ .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
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},
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{
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.compatible = "marvell,mv78200-gpio",
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- .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
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+ .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
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},
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{
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.compatible = "marvell,armadaxp-gpio",
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- .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
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+ .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
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},
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{
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/* sentinel */
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@@ -668,7 +674,8 @@ static int mvebu_gpio_probe(struct platf
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else
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soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
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- mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL);
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+ mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
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+ GFP_KERNEL);
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if (!mvchip)
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return -ENOMEM;
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@@ -767,8 +774,8 @@ static int mvebu_gpio_probe(struct platf
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* interrupt handlers, with each handler dealing with 8 GPIO
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* pins. */
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for (i = 0; i < 4; i++) {
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- int irq;
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- irq = platform_get_irq(pdev, i);
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+ int irq = platform_get_irq(pdev, i);
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+
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if (irq < 0)
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continue;
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irq_set_handler_data(irq, mvchip);
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@@ -827,7 +834,7 @@ static int mvebu_gpio_probe(struct platf
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static struct platform_driver mvebu_gpio_driver = {
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.driver = {
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- .name = "mvebu-gpio",
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+ .name = "mvebu-gpio",
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.of_match_table = mvebu_gpio_of_match,
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},
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.probe = mvebu_gpio_probe,
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