mirror of https://github.com/hak5/openwrt.git
1040 lines
34 KiB
Diff
1040 lines
34 KiB
Diff
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From 688c075ddc08723848df01fc0426d69d0b3a464b Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 29 Sep 2011 17:16:38 +0200
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Subject: [PATCH 46/73] MIPS: lantiq: adds GPTU driver
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---
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arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++
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arch/mips/lantiq/xway/Makefile | 2 +-
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arch/mips/lantiq/xway/sysctrl.c | 1 +
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arch/mips/lantiq/xway/timer.c | 846 ++++++++++++++++++++++
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4 files changed, 1003 insertions(+), 1 deletions(-)
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create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h
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create mode 100644 arch/mips/lantiq/xway/timer.c
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
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@@ -0,0 +1,155 @@
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+#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
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+#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
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+
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+
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+/******************************************************************************
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+ Copyright (c) 2002, Infineon Technologies. All rights reserved.
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+
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+ No Warranty
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+ Because the program is licensed free of charge, there is no warranty for
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+ the program, to the extent permitted by applicable law. Except when
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+ otherwise stated in writing the copyright holders and/or other parties
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+ provide the program "as is" without warranty of any kind, either
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+ expressed or implied, including, but not limited to, the implied
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+ warranties of merchantability and fitness for a particular purpose. The
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+ entire risk as to the quality and performance of the program is with
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+ you. should the program prove defective, you assume the cost of all
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+ necessary servicing, repair or correction.
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+
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+ In no event unless required by applicable law or agreed to in writing
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+ will any copyright holder, or any other party who may modify and/or
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+ redistribute the program as permitted above, be liable to you for
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+ damages, including any general, special, incidental or consequential
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+ damages arising out of the use or inability to use the program
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+ (including but not limited to loss of data or data being rendered
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+ inaccurate or losses sustained by you or third parties or a failure of
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+ the program to operate with any other programs), even if such holder or
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+ other party has been advised of the possibility of such damages.
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+******************************************************************************/
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+
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+
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+/*
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+ * ####################################
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+ * Definition
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+ * ####################################
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+ */
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+
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+/*
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+ * Available Timer/Counter Index
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+ */
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+#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
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+#define TIMER_ANY 0x00
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+#define TIMER1A TIMER(1, 0)
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+#define TIMER1B TIMER(1, 1)
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+#define TIMER2A TIMER(2, 0)
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+#define TIMER2B TIMER(2, 1)
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+#define TIMER3A TIMER(3, 0)
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+#define TIMER3B TIMER(3, 1)
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+
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+/*
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+ * Flag of Timer/Counter
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+ * These flags specify the way in which timer is configured.
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+ */
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+/* Bit size of timer/counter. */
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+#define TIMER_FLAG_16BIT 0x0000
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+#define TIMER_FLAG_32BIT 0x0001
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+/* Switch between timer and counter. */
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+#define TIMER_FLAG_TIMER 0x0000
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+#define TIMER_FLAG_COUNTER 0x0002
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+/* Stop or continue when overflowing/underflowing. */
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+#define TIMER_FLAG_ONCE 0x0000
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+#define TIMER_FLAG_CYCLIC 0x0004
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+/* Count up or counter down. */
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+#define TIMER_FLAG_UP 0x0000
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+#define TIMER_FLAG_DOWN 0x0008
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+/* Count on specific level or edge. */
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+#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
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+#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
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+#define TIMER_FLAG_RISE_EDGE 0x0010
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+#define TIMER_FLAG_FALL_EDGE 0x0020
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+#define TIMER_FLAG_ANY_EDGE 0x0030
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+/* Signal is syncronous to module clock or not. */
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+#define TIMER_FLAG_UNSYNC 0x0000
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+#define TIMER_FLAG_SYNC 0x0080
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+/* Different interrupt handle type. */
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+#define TIMER_FLAG_NO_HANDLE 0x0000
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+#if defined(__KERNEL__)
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+ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
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+#endif // defined(__KERNEL__)
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+#define TIMER_FLAG_SIGNAL 0x0300
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+/* Internal clock source or external clock source */
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+#define TIMER_FLAG_INT_SRC 0x0000
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+#define TIMER_FLAG_EXT_SRC 0x1000
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+
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+
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+/*
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+ * ioctl Command
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+ */
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+#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
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+#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
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+#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
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+#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
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+#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
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+#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
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+#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
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+#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
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+
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+/*
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+ * Data Type Used to Call ioctl
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+ */
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+struct gptu_ioctl_param {
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+ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
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+ * GPTU_SET_COUNTER, this field is ID of expected *
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+ * timer/counter. If it's zero, a timer/counter would *
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+ * be dynamically allocated and ID would be stored in *
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+ * this field. *
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+ * In command GPTU_GET_COUNT_VALUE, this field is *
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+ * ignored. *
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+ * In other command, this field is ID of timer/counter *
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+ * allocated. */
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+ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
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+ * GPTU_SET_COUNTER, this field contains flags to *
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+ * specify how to configure timer/counter. *
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+ * In command GPTU_START_TIMER, zero indicate start *
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+ * and non-zero indicate resume timer/counter. *
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+ * In other command, this field is ignored. */
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+ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
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+ * init/reload value. *
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+ * In command GPTU_SET_TIMER, this field contains *
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+ * frequency (0.001Hz) of timer. *
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+ * In command GPTU_GET_COUNT_VALUE, current count *
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+ * value would be stored in this field. *
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+ * In command GPTU_CALCULATE_DIVIDER, this field *
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+ * contains frequency wanted, and after calculation, *
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+ * divider would be stored in this field to overwrite *
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+ * the frequency. *
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+ * In other command, this field is ignored. */
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+ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
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+ * if signal is required, this field contains process *
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+ * ID to which signal would be sent. *
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+ * In other command, this field is ignored. */
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+ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
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+ * if signal is required, this field contains signal *
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+ * number which would be sent. *
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+ * In other command, this field is ignored. */
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+};
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+
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+/*
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+ * ####################################
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+ * Data Type
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+ * ####################################
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+ */
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+typedef void (*timer_callback)(unsigned long arg);
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+
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+extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
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+extern int lq_free_timer(unsigned int);
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+extern int lq_start_timer(unsigned int, int);
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+extern int lq_stop_timer(unsigned int);
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+extern int lq_reset_counter_flags(u32 timer, u32 flags);
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+extern int lq_get_count_value(unsigned int, unsigned long *);
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+extern u32 lq_cal_divider(unsigned long);
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+extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
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+extern int lq_set_counter(unsigned int timer, unsigned int flag,
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+ u32 reload, unsigned long arg1, unsigned long arg2);
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+
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+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
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--- a/arch/mips/lantiq/xway/Makefile
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+++ b/arch/mips/lantiq/xway/Makefile
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@@ -1,4 +1,4 @@
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-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o
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+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o timer.o
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obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
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obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -147,6 +147,7 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
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clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
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clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
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+ clkdev_add_pmu("ltq_gptu", NULL, 0, PMU_GPT);
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if (!ltq_is_vr9())
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clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
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if (ltq_is_ase()) {
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--- /dev/null
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+++ b/arch/mips/lantiq/xway/timer.c
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@@ -0,0 +1,846 @@
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/version.h>
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+#include <linux/types.h>
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+#include <linux/fs.h>
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+#include <linux/miscdevice.h>
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+#include <linux/init.h>
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+#include <linux/uaccess.h>
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+#include <linux/unistd.h>
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+#include <linux/errno.h>
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+#include <linux/interrupt.h>
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+#include <linux/sched.h>
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+
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+#include <asm/irq.h>
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+#include <asm/div64.h>
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+#include "../clk.h"
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+
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+#include <lantiq_soc.h>
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+#include <lantiq_irq.h>
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+#include <lantiq_timer.h>
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+
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+#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
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+
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+#ifdef TIMER1A
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+#define FIRST_TIMER TIMER1A
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+#else
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+#define FIRST_TIMER 2
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+#endif
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+
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+/*
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+ * GPTC divider is set or not.
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+ */
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+#define GPTU_CLC_RMC_IS_SET 0
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+
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+/*
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+ * Timer Interrupt (IRQ)
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+ */
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+/* Must be adjusted when ICU driver is available */
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+#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
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+
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+/*
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+ * Bits Operation
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+ */
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+#define GET_BITS(x, msb, lsb) \
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+ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
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+#define SET_BITS(x, msb, lsb, value) \
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+ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
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+ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
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+
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+/*
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+ * GPTU Register Mapping
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+ */
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+#define LQ_GPTU (KSEG1 + 0x1E100A00)
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+#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000))
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+#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008))
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+#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
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+#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
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+#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
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+#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
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+#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4))
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+#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8))
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+#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC))
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+
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+/*
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+ * Clock Control Register
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+ */
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+#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16)
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+#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8)
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+#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5))
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+#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3))
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+#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2))
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+#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1))
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+#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0))
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+
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+#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
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+#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
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+#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
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+#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
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+#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
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+#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
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+#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
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+
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+/*
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+ * ID Register
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+ */
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+#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8)
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+#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5)
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+#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0)
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+
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+/*
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+ * Control Register of Timer/Counter nX
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+ * n is the index of block (1 based index)
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+ * X is either A or B
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+ */
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+#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10))
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+#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9))
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+#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8))
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+#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
|
||
|
|
+#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5))
|
||
|
|
+#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
|
||
|
|
+#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3))
|
||
|
|
+#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2))
|
||
|
|
+#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1))
|
||
|
|
+#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0))
|
||
|
|
+
|
||
|
|
+#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
|
||
|
|
+#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
|
||
|
|
+#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
|
||
|
|
+#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
|
||
|
|
+#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
|
||
|
|
+#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
|
||
|
|
+#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
|
||
|
|
+#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
|
||
|
|
+#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
|
||
|
|
+
|
||
|
|
+#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
|
||
|
|
+#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
|
||
|
|
+#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
|
||
|
|
+
|
||
|
|
+#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
|
||
|
|
+#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
|
||
|
|
+
|
||
|
|
+#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
|
||
|
|
+#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
|
||
|
|
+#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
|
||
|
|
+#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
|
||
|
|
+#define TIMER_FLAG_NONE_EDGE 0x0000
|
||
|
|
+#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
|
||
|
|
+#define TIMER_FLAG_REAL 0x0000
|
||
|
|
+#define TIMER_FLAG_INVERT 0x0040
|
||
|
|
+#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
|
||
|
|
+#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
|
||
|
|
+#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
|
||
|
|
+#define TIMER_FLAG_CALLBACK_IN_HB 0x0200
|
||
|
|
+#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
|
||
|
|
+#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
|
||
|
|
+
|
||
|
|
+struct timer_dev_timer {
|
||
|
|
+ unsigned int f_irq_on;
|
||
|
|
+ unsigned int irq;
|
||
|
|
+ unsigned int flag;
|
||
|
|
+ unsigned long arg1;
|
||
|
|
+ unsigned long arg2;
|
||
|
|
+};
|
||
|
|
+
|
||
|
|
+struct timer_dev {
|
||
|
|
+ struct mutex gptu_mutex;
|
||
|
|
+ unsigned int number_of_timers;
|
||
|
|
+ unsigned int occupation;
|
||
|
|
+ unsigned int f_gptu_on;
|
||
|
|
+ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
|
||
|
|
+};
|
||
|
|
+
|
||
|
|
+unsigned long ltq_danube_fpi_bus_clock(int fpi);
|
||
|
|
+unsigned long ltq_vr9_fpi_bus_clock(int fpi);
|
||
|
|
+
|
||
|
|
+unsigned int ltq_get_fpi_bus_clock(int fpi) {
|
||
|
|
+ if (ltq_is_ase())
|
||
|
|
+ return CLOCK_133M;
|
||
|
|
+ else if (ltq_is_vr9())
|
||
|
|
+ return ltq_vr9_fpi_bus_clock(fpi);
|
||
|
|
+
|
||
|
|
+ return ltq_danube_fpi_bus_clock(fpi);
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+
|
||
|
|
+static long gptu_ioctl(struct file *, unsigned int, unsigned long);
|
||
|
|
+static int gptu_open(struct inode *, struct file *);
|
||
|
|
+static int gptu_release(struct inode *, struct file *);
|
||
|
|
+
|
||
|
|
+static struct file_operations gptu_fops = {
|
||
|
|
+ .owner = THIS_MODULE,
|
||
|
|
+ .unlocked_ioctl = gptu_ioctl,
|
||
|
|
+ .open = gptu_open,
|
||
|
|
+ .release = gptu_release
|
||
|
|
+};
|
||
|
|
+
|
||
|
|
+static struct miscdevice gptu_miscdev = {
|
||
|
|
+ .minor = MISC_DYNAMIC_MINOR,
|
||
|
|
+ .name = "gptu",
|
||
|
|
+ .fops = &gptu_fops,
|
||
|
|
+};
|
||
|
|
+
|
||
|
|
+static struct timer_dev timer_dev;
|
||
|
|
+
|
||
|
|
+static irqreturn_t timer_irq_handler(int irq, void *p)
|
||
|
|
+{
|
||
|
|
+ unsigned int timer;
|
||
|
|
+ unsigned int flag;
|
||
|
|
+ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
|
||
|
|
+
|
||
|
|
+ timer = irq - TIMER_INTERRUPT;
|
||
|
|
+ if (timer < timer_dev.number_of_timers
|
||
|
|
+ && dev_timer == &timer_dev.timer[timer]) {
|
||
|
|
+ /* Clear interrupt. */
|
||
|
|
+ ltq_w32(1 << timer, LQ_GPTU_IRNCR);
|
||
|
|
+
|
||
|
|
+ /* Call user hanler or signal. */
|
||
|
|
+ flag = dev_timer->flag;
|
||
|
|
+ if (!(timer & 0x01)
|
||
|
|
+ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
|
||
|
|
+ /* 16-bit timer or timer A of 32-bit timer */
|
||
|
|
+ switch (TIMER_FLAG_MASK_HANDLE(flag)) {
|
||
|
|
+ case TIMER_FLAG_CALLBACK_IN_IRQ:
|
||
|
|
+ case TIMER_FLAG_CALLBACK_IN_HB:
|
||
|
|
+ if (dev_timer->arg1)
|
||
|
|
+ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
|
||
|
|
+ break;
|
||
|
|
+ case TIMER_FLAG_SIGNAL:
|
||
|
|
+ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
|
||
|
|
+ break;
|
||
|
|
+ }
|
||
|
|
+ }
|
||
|
|
+ }
|
||
|
|
+ return IRQ_HANDLED;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+static inline void lq_enable_gptu(void)
|
||
|
|
+{
|
||
|
|
+ struct clk *clk = clk_get_sys("ltq_gptu", NULL);
|
||
|
|
+ clk_enable(clk);
|
||
|
|
+
|
||
|
|
+ //ltq_pmu_enable(PMU_GPT);
|
||
|
|
+
|
||
|
|
+ /* Set divider as 1, disable write protection for SPEN, enable module. */
|
||
|
|
+ *LQ_GPTU_CLC =
|
||
|
|
+ GPTU_CLC_SMC_SET(0x00) |
|
||
|
|
+ GPTU_CLC_RMC_SET(0x01) |
|
||
|
|
+ GPTU_CLC_FSOE_SET(0) |
|
||
|
|
+ GPTU_CLC_SBWE_SET(1) |
|
||
|
|
+ GPTU_CLC_EDIS_SET(0) |
|
||
|
|
+ GPTU_CLC_SPEN_SET(0) |
|
||
|
|
+ GPTU_CLC_DISR_SET(0);
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+static inline void lq_disable_gptu(void)
|
||
|
|
+{
|
||
|
|
+ struct clk *clk = clk_get_sys("ltq_gptu", NULL);
|
||
|
|
+ ltq_w32(0x00, LQ_GPTU_IRNEN);
|
||
|
|
+ ltq_w32(0xfff, LQ_GPTU_IRNCR);
|
||
|
|
+
|
||
|
|
+ /* Set divider as 0, enable write protection for SPEN, disable module. */
|
||
|
|
+ *LQ_GPTU_CLC =
|
||
|
|
+ GPTU_CLC_SMC_SET(0x00) |
|
||
|
|
+ GPTU_CLC_RMC_SET(0x00) |
|
||
|
|
+ GPTU_CLC_FSOE_SET(0) |
|
||
|
|
+ GPTU_CLC_SBWE_SET(0) |
|
||
|
|
+ GPTU_CLC_EDIS_SET(0) |
|
||
|
|
+ GPTU_CLC_SPEN_SET(0) |
|
||
|
|
+ GPTU_CLC_DISR_SET(1);
|
||
|
|
+
|
||
|
|
+ clk_enable(clk);
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+int lq_request_timer(unsigned int timer, unsigned int flag,
|
||
|
|
+ unsigned long value, unsigned long arg1, unsigned long arg2)
|
||
|
|
+{
|
||
|
|
+ int ret = 0;
|
||
|
|
+ unsigned int con_reg, irnen_reg;
|
||
|
|
+ int n, X;
|
||
|
|
+
|
||
|
|
+ if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
|
||
|
|
+ return -EINVAL;
|
||
|
|
+
|
||
|
|
+ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
|
||
|
|
+ timer, flag, value);
|
||
|
|
+
|
||
|
|
+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
|
||
|
|
+ value &= 0xFFFF;
|
||
|
|
+ else
|
||
|
|
+ timer &= ~0x01;
|
||
|
|
+
|
||
|
|
+ mutex_lock(&timer_dev.gptu_mutex);
|
||
|
|
+
|
||
|
|
+ /*
|
||
|
|
+ * Allocate timer.
|
||
|
|
+ */
|
||
|
|
+ if (timer < FIRST_TIMER) {
|
||
|
|
+ unsigned int mask;
|
||
|
|
+ unsigned int shift;
|
||
|
|
+ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
|
||
|
|
+ unsigned int offset = TIMER2A;
|
||
|
|
+
|
||
|
|
+ /*
|
||
|
|
+ * Pick up a free timer.
|
||
|
|
+ */
|
||
|
|
+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
|
||
|
|
+ mask = 1 << offset;
|
||
|
|
+ shift = 1;
|
||
|
|
+ } else {
|
||
|
|
+ mask = 3 << offset;
|
||
|
|
+ shift = 2;
|
||
|
|
+ }
|
||
|
|
+ for (timer = offset;
|
||
|
|
+ timer < offset + timer_dev.number_of_timers;
|
||
|
|
+ timer += shift, mask <<= shift)
|
||
|
|
+ if (!(timer_dev.occupation & mask)) {
|
||
|
|
+ timer_dev.occupation |= mask;
|
||
|
|
+ break;
|
||
|
|
+ }
|
||
|
|
+ if (timer >= offset + timer_dev.number_of_timers) {
|
||
|
|
+ printk("failed![%d]\n", __LINE__);
|
||
|
|
+ mutex_unlock(&timer_dev.gptu_mutex);
|
||
|
|
+ return -EINVAL;
|
||
|
|
+ } else
|
||
|
|
+ ret = timer;
|
||
|
|
+ } else {
|
||
|
|
+ register unsigned int mask;
|
||
|
|
+
|
||
|
|
+ /*
|
||
|
|
+ * Check if the requested timer is free.
|
||
|
|
+ */
|
||
|
|
+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
|
||
|
|
+ if ((timer_dev.occupation & mask)) {
|
||
|
|
+ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
|
||
|
|
+ __LINE__, mask, timer_dev.occupation);
|
||
|
|
+ mutex_unlock(&timer_dev.gptu_mutex);
|
||
|
|
+ return -EBUSY;
|
||
|
|
+ } else {
|
||
|
|
+ timer_dev.occupation |= mask;
|
||
|
|
+ ret = 0;
|
||
|
|
+ }
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ /*
|
||
|
|
+ * Prepare control register value.
|
||
|
|
+ */
|
||
|
|
+ switch (TIMER_FLAG_MASK_EDGE(flag)) {
|
||
|
|
+ default:
|
||
|
|
+ case TIMER_FLAG_NONE_EDGE:
|
||
|
|
+ con_reg = GPTU_CON_EDGE_SET(0x00);
|
||
|
|
+ break;
|
||
|
|
+ case TIMER_FLAG_RISE_EDGE:
|
||
|
|
+ con_reg = GPTU_CON_EDGE_SET(0x01);
|
||
|
|
+ break;
|
||
|
|
+ case TIMER_FLAG_FALL_EDGE:
|
||
|
|
+ con_reg = GPTU_CON_EDGE_SET(0x02);
|
||
|
|
+ break;
|
||
|
|
+ case TIMER_FLAG_ANY_EDGE:
|
||
|
|
+ con_reg = GPTU_CON_EDGE_SET(0x03);
|
||
|
|
+ break;
|
||
|
|
+ }
|
||
|
|
+ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
|
||
|
|
+ con_reg |=
|
||
|
|
+ TIMER_FLAG_MASK_SRC(flag) ==
|
||
|
|
+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
|
||
|
|
+ GPTU_CON_SRC_EXT_SET(0);
|
||
|
|
+ else
|
||
|
|
+ con_reg |=
|
||
|
|
+ TIMER_FLAG_MASK_SRC(flag) ==
|
||
|
|
+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
|
||
|
|
+ GPTU_CON_SRC_EG_SET(0);
|
||
|
|
+ con_reg |=
|
||
|
|
+ TIMER_FLAG_MASK_SYNC(flag) ==
|
||
|
|
+ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
|
||
|
|
+ GPTU_CON_SYNC_SET(1);
|
||
|
|
+ con_reg |=
|
||
|
|
+ TIMER_FLAG_MASK_INVERT(flag) ==
|
||
|
|
+ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
|
||
|
|
+ con_reg |=
|
||
|
|
+ TIMER_FLAG_MASK_SIZE(flag) ==
|
||
|
|
+ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
|
||
|
|
+ GPTU_CON_EXT_SET(1);
|
||
|
|
+ con_reg |=
|
||
|
|
+ TIMER_FLAG_MASK_STOP(flag) ==
|
||
|
|
+ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
|
||
|
|
+ con_reg |=
|
||
|
|
+ TIMER_FLAG_MASK_TYPE(flag) ==
|
||
|
|
+ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
|
||
|
|
+ GPTU_CON_CNT_SET(1);
|
||
|
|
+ con_reg |=
|
||
|
|
+ TIMER_FLAG_MASK_DIR(flag) ==
|
||
|
|
+ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
|
||
|
|
+
|
||
|
|
+ /*
|
||
|
|
+ * Fill up running data.
|
||
|
|
+ */
|
||
|
|
+ timer_dev.timer[timer - FIRST_TIMER].flag = flag;
|
||
|
|
+ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
|
||
|
|
+ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
|
||
|
|
+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
|
||
|
|
+ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
|
||
|
|
+
|
||
|
|
+ /*
|
||
|
|
+ * Enable GPTU module.
|
||
|
|
+ */
|
||
|
|
+ if (!timer_dev.f_gptu_on) {
|
||
|
|
+ lq_enable_gptu();
|
||
|
|
+ timer_dev.f_gptu_on = 1;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ /*
|
||
|
|
+ * Enable IRQ.
|
||
|
|
+ */
|
||
|
|
+ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
|
||
|
|
+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
|
||
|
|
+ timer_dev.timer[timer - FIRST_TIMER].arg1 =
|
||
|
|
+ (unsigned long) find_task_by_vpid((int) arg1);
|
||
|
|
+
|
||
|
|
+ irnen_reg = 1 << (timer - FIRST_TIMER);
|
||
|
|
+
|
||
|
|
+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
|
||
|
|
+ || (TIMER_FLAG_MASK_HANDLE(flag) ==
|
||
|
|
+ TIMER_FLAG_CALLBACK_IN_IRQ
|
||
|
|
+ && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
|
||
|
|
+ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
|
||
|
|
+ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
|
||
|
|
+ }
|
||
|
|
+ } else
|
||
|
|
+ irnen_reg = 0;
|
||
|
|
+
|
||
|
|
+ /*
|
||
|
|
+ * Write config register, reload value and enable interrupt.
|
||
|
|
+ */
|
||
|
|
+ n = timer >> 1;
|
||
|
|
+ X = timer & 0x01;
|
||
|
|
+ *LQ_GPTU_CON(n, X) = con_reg;
|
||
|
|
+ *LQ_GPTU_RELOAD(n, X) = value;
|
||
|
|
+ /* printk("reload value = %d\n", (u32)value); */
|
||
|
|
+ *LQ_GPTU_IRNEN |= irnen_reg;
|
||
|
|
+
|
||
|
|
+ mutex_unlock(&timer_dev.gptu_mutex);
|
||
|
|
+ printk("successful!\n");
|
||
|
|
+ return ret;
|
||
|
|
+}
|
||
|
|
+EXPORT_SYMBOL(lq_request_timer);
|
||
|
|
+
|
||
|
|
+int lq_free_timer(unsigned int timer)
|
||
|
|
+{
|
||
|
|
+ unsigned int flag;
|
||
|
|
+ unsigned int mask;
|
||
|
|
+ int n, X;
|
||
|
|
+
|
||
|
|
+ if (!timer_dev.f_gptu_on)
|
||
|
|
+ return -EINVAL;
|
||
|
|
+
|
||
|
|
+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
|
||
|
|
+ return -EINVAL;
|
||
|
|
+
|
||
|
|
+ mutex_lock(&timer_dev.gptu_mutex);
|
||
|
|
+
|
||
|
|
+ flag = timer_dev.timer[timer - FIRST_TIMER].flag;
|
||
|
|
+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
|
||
|
|
+ timer &= ~0x01;
|
||
|
|
+
|
||
|
|
+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
|
||
|
|
+ if (((timer_dev.occupation & mask) ^ mask)) {
|
||
|
|
+ mutex_unlock(&timer_dev.gptu_mutex);
|
||
|
|
+ return -EINVAL;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ n = timer >> 1;
|
||
|
|
+ X = timer & 0x01;
|
||
|
|
+
|
||
|
|
+ if (GPTU_CON_EN(n, X))
|
||
|
|
+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
|
||
|
|
+
|
||
|
|
+ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
|
||
|
|
+ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
|
||
|
|
+
|
||
|
|
+ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
|
||
|
|
+ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
|
||
|
|
+ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ timer_dev.occupation &= ~mask;
|
||
|
|
+ if (!timer_dev.occupation && timer_dev.f_gptu_on) {
|
||
|
|
+ lq_disable_gptu();
|
||
|
|
+ timer_dev.f_gptu_on = 0;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ mutex_unlock(&timer_dev.gptu_mutex);
|
||
|
|
+
|
||
|
|
+ return 0;
|
||
|
|
+}
|
||
|
|
+EXPORT_SYMBOL(lq_free_timer);
|
||
|
|
+
|
||
|
|
+int lq_start_timer(unsigned int timer, int is_resume)
|
||
|
|
+{
|
||
|
|
+ unsigned int flag;
|
||
|
|
+ unsigned int mask;
|
||
|
|
+ int n, X;
|
||
|
|
+
|
||
|
|
+ if (!timer_dev.f_gptu_on)
|
||
|
|
+ return -EINVAL;
|
||
|
|
+
|
||
|
|
+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
|
||
|
|
+ return -EINVAL;
|
||
|
|
+
|
||
|
|
+ mutex_lock(&timer_dev.gptu_mutex);
|
||
|
|
+
|
||
|
|
+ flag = timer_dev.timer[timer - FIRST_TIMER].flag;
|
||
|
|
+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
|
||
|
|
+ timer &= ~0x01;
|
||
|
|
+
|
||
|
|
+ mask = (TIMER_FLAG_MASK_SIZE(flag) ==
|
||
|
|
+ TIMER_FLAG_16BIT ? 1 : 3) << timer;
|
||
|
|
+ if (((timer_dev.occupation & mask) ^ mask)) {
|
||
|
|
+ mutex_unlock(&timer_dev.gptu_mutex);
|
||
|
|
+ return -EINVAL;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ n = timer >> 1;
|
||
|
|
+ X = timer & 0x01;
|
||
|
|
+
|
||
|
|
+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
|
||
|
|
+
|
||
|
|
+ mutex_unlock(&timer_dev.gptu_mutex);
|
||
|
|
+
|
||
|
|
+ return 0;
|
||
|
|
+}
|
||
|
|
+EXPORT_SYMBOL(lq_start_timer);
|
||
|
|
+
|
||
|
|
+int lq_stop_timer(unsigned int timer)
|
||
|
|
+{
|
||
|
|
+ unsigned int flag;
|
||
|
|
+ unsigned int mask;
|
||
|
|
+ int n, X;
|
||
|
|
+
|
||
|
|
+ if (!timer_dev.f_gptu_on)
|
||
|
|
+ return -EINVAL;
|
||
|
|
+
|
||
|
|
+ if (timer < FIRST_TIMER
|
||
|
|
+ || timer >= FIRST_TIMER + timer_dev.number_of_timers)
|
||
|
|
+ return -EINVAL;
|
||
|
|
+
|
||
|
|
+ mutex_lock(&timer_dev.gptu_mutex);
|
||
|
|
+
|
||
|
|
+ flag = timer_dev.timer[timer - FIRST_TIMER].flag;
|
||
|
|
+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
|
||
|
|
+ timer &= ~0x01;
|
||
|
|
+
|
||
|
|
+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
|
||
|
|
+ if (((timer_dev.occupation & mask) ^ mask)) {
|
||
|
|
+ mutex_unlock(&timer_dev.gptu_mutex);
|
||
|
|
+ return -EINVAL;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ n = timer >> 1;
|
||
|
|
+ X = timer & 0x01;
|
||
|
|
+
|
||
|
|
+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
|
||
|
|
+
|
||
|
|
+ mutex_unlock(&timer_dev.gptu_mutex);
|
||
|
|
+
|
||
|
|
+ return 0;
|
||
|
|
+}
|
||
|
|
+EXPORT_SYMBOL(lq_stop_timer);
|
||
|
|
+
|
||
|
|
+int lq_reset_counter_flags(u32 timer, u32 flags)
|
||
|
|
+{
|
||
|
|
+ unsigned int oflag;
|
||
|
|
+ unsigned int mask, con_reg;
|
||
|
|
+ int n, X;
|
||
|
|
+
|
||
|
|
+ if (!timer_dev.f_gptu_on)
|
||
|
|
+ return -EINVAL;
|
||
|
|
+
|
||
|
|
+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
|
||
|
|
+ return -EINVAL;
|
||
|
|
+
|
||
|
|
+ mutex_lock(&timer_dev.gptu_mutex);
|
||
|
|
+
|
||
|
|
+ oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
|
||
|
|
+ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
|
||
|
|
+ timer &= ~0x01;
|
||
|
|
+
|
||
|
|
+ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
|
||
|
|
+ if (((timer_dev.occupation & mask) ^ mask)) {
|
||
|
|
+ mutex_unlock(&timer_dev.gptu_mutex);
|
||
|
|
+ return -EINVAL;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ switch (TIMER_FLAG_MASK_EDGE(flags)) {
|
||
|
|
+ default:
|
||
|
|
+ case TIMER_FLAG_NONE_EDGE:
|
||
|
|
+ con_reg = GPTU_CON_EDGE_SET(0x00);
|
||
|
|
+ break;
|
||
|
|
+ case TIMER_FLAG_RISE_EDGE:
|
||
|
|
+ con_reg = GPTU_CON_EDGE_SET(0x01);
|
||
|
|
+ break;
|
||
|
|
+ case TIMER_FLAG_FALL_EDGE:
|
||
|
|
+ con_reg = GPTU_CON_EDGE_SET(0x02);
|
||
|
|
+ break;
|
||
|
|
+ case TIMER_FLAG_ANY_EDGE:
|
||
|
|
+ con_reg = GPTU_CON_EDGE_SET(0x03);
|
||
|
|
+ break;
|
||
|
|
+ }
|
||
|
|
+ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
|
||
|
|
+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
|
||
|
|
+ else
|
||
|
|
+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
|
||
|
|
+ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
|
||
|
|
+ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
|
||
|
|
+ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
|
||
|
|
+ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
|
||
|
|
+ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
|
||
|
|
+ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
|
||
|
|
+
|
||
|
|
+ timer_dev.timer[timer - FIRST_TIMER].flag = flags;
|
||
|
|
+ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
|
||
|
|
+ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
|
||
|
|
+
|
||
|
|
+ n = timer >> 1;
|
||
|
|
+ X = timer & 0x01;
|
||
|
|
+
|
||
|
|
+ *LQ_GPTU_CON(n, X) = con_reg;
|
||
|
|
+ smp_wmb();
|
||
|
|
+ printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X));
|
||
|
|
+ mutex_unlock(&timer_dev.gptu_mutex);
|
||
|
|
+ return 0;
|
||
|
|
+}
|
||
|
|
+EXPORT_SYMBOL(lq_reset_counter_flags);
|
||
|
|
+
|
||
|
|
+int lq_get_count_value(unsigned int timer, unsigned long *value)
|
||
|
|
+{
|
||
|
|
+ unsigned int flag;
|
||
|
|
+ unsigned int mask;
|
||
|
|
+ int n, X;
|
||
|
|
+
|
||
|
|
+ if (!timer_dev.f_gptu_on)
|
||
|
|
+ return -EINVAL;
|
||
|
|
+
|
||
|
|
+ if (timer < FIRST_TIMER
|
||
|
|
+ || timer >= FIRST_TIMER + timer_dev.number_of_timers)
|
||
|
|
+ return -EINVAL;
|
||
|
|
+
|
||
|
|
+ mutex_lock(&timer_dev.gptu_mutex);
|
||
|
|
+
|
||
|
|
+ flag = timer_dev.timer[timer - FIRST_TIMER].flag;
|
||
|
|
+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
|
||
|
|
+ timer &= ~0x01;
|
||
|
|
+
|
||
|
|
+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
|
||
|
|
+ if (((timer_dev.occupation & mask) ^ mask)) {
|
||
|
|
+ mutex_unlock(&timer_dev.gptu_mutex);
|
||
|
|
+ return -EINVAL;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ n = timer >> 1;
|
||
|
|
+ X = timer & 0x01;
|
||
|
|
+
|
||
|
|
+ *value = *LQ_GPTU_COUNT(n, X);
|
||
|
|
+
|
||
|
|
+ mutex_unlock(&timer_dev.gptu_mutex);
|
||
|
|
+
|
||
|
|
+ return 0;
|
||
|
|
+}
|
||
|
|
+EXPORT_SYMBOL(lq_get_count_value);
|
||
|
|
+
|
||
|
|
+u32 lq_cal_divider(unsigned long freq)
|
||
|
|
+{
|
||
|
|
+ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
|
||
|
|
+ u32 clock_divider = 1;
|
||
|
|
+ module_freq = fpi * 1000;
|
||
|
|
+ do_div(module_freq, clock_divider * freq);
|
||
|
|
+ return module_freq;
|
||
|
|
+}
|
||
|
|
+EXPORT_SYMBOL(lq_cal_divider);
|
||
|
|
+
|
||
|
|
+int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
|
||
|
|
+ int is_ext_src, unsigned int handle_flag, unsigned long arg1,
|
||
|
|
+ unsigned long arg2)
|
||
|
|
+{
|
||
|
|
+ unsigned long divider;
|
||
|
|
+ unsigned int flag;
|
||
|
|
+
|
||
|
|
+ divider = lq_cal_divider(freq);
|
||
|
|
+ if (divider == 0)
|
||
|
|
+ return -EINVAL;
|
||
|
|
+ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
|
||
|
|
+ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
|
||
|
|
+ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
|
||
|
|
+ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
|
||
|
|
+ | TIMER_FLAG_MASK_HANDLE(handle_flag);
|
||
|
|
+
|
||
|
|
+ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
|
||
|
|
+ timer, freq, divider);
|
||
|
|
+ return lq_request_timer(timer, flag, divider, arg1, arg2);
|
||
|
|
+}
|
||
|
|
+EXPORT_SYMBOL(lq_set_timer);
|
||
|
|
+
|
||
|
|
+int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
|
||
|
|
+ unsigned long arg1, unsigned long arg2)
|
||
|
|
+{
|
||
|
|
+ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
|
||
|
|
+ return lq_request_timer(timer, flag, reload, arg1, arg2);
|
||
|
|
+}
|
||
|
|
+EXPORT_SYMBOL(lq_set_counter);
|
||
|
|
+
|
||
|
|
+static long gptu_ioctl(struct file *file, unsigned int cmd,
|
||
|
|
+ unsigned long arg)
|
||
|
|
+{
|
||
|
|
+ int ret;
|
||
|
|
+ struct gptu_ioctl_param param;
|
||
|
|
+
|
||
|
|
+ if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
|
||
|
|
+ return -EFAULT;
|
||
|
|
+ copy_from_user(¶m, (void *) arg, sizeof(param));
|
||
|
|
+
|
||
|
|
+ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
|
||
|
|
+ || GPTU_SET_COUNTER) && param.timer < 2)
|
||
|
|
+ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
|
||
|
|
+ && !access_ok(VERIFY_WRITE, arg,
|
||
|
|
+ sizeof(struct gptu_ioctl_param)))
|
||
|
|
+ return -EFAULT;
|
||
|
|
+
|
||
|
|
+ switch (cmd) {
|
||
|
|
+ case GPTU_REQUEST_TIMER:
|
||
|
|
+ ret = lq_request_timer(param.timer, param.flag, param.value,
|
||
|
|
+ (unsigned long) param.pid,
|
||
|
|
+ (unsigned long) param.sig);
|
||
|
|
+ if (ret > 0) {
|
||
|
|
+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
|
||
|
|
+ timer, &ret, sizeof(&ret));
|
||
|
|
+ ret = 0;
|
||
|
|
+ }
|
||
|
|
+ break;
|
||
|
|
+ case GPTU_FREE_TIMER:
|
||
|
|
+ ret = lq_free_timer(param.timer);
|
||
|
|
+ break;
|
||
|
|
+ case GPTU_START_TIMER:
|
||
|
|
+ ret = lq_start_timer(param.timer, param.flag);
|
||
|
|
+ break;
|
||
|
|
+ case GPTU_STOP_TIMER:
|
||
|
|
+ ret = lq_stop_timer(param.timer);
|
||
|
|
+ break;
|
||
|
|
+ case GPTU_GET_COUNT_VALUE:
|
||
|
|
+ ret = lq_get_count_value(param.timer, ¶m.value);
|
||
|
|
+ if (!ret)
|
||
|
|
+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
|
||
|
|
+ value, ¶m.value,
|
||
|
|
+ sizeof(param.value));
|
||
|
|
+ break;
|
||
|
|
+ case GPTU_CALCULATE_DIVIDER:
|
||
|
|
+ param.value = lq_cal_divider(param.value);
|
||
|
|
+ if (param.value == 0)
|
||
|
|
+ ret = -EINVAL;
|
||
|
|
+ else {
|
||
|
|
+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
|
||
|
|
+ value, ¶m.value,
|
||
|
|
+ sizeof(param.value));
|
||
|
|
+ ret = 0;
|
||
|
|
+ }
|
||
|
|
+ break;
|
||
|
|
+ case GPTU_SET_TIMER:
|
||
|
|
+ ret = lq_set_timer(param.timer, param.value,
|
||
|
|
+ TIMER_FLAG_MASK_STOP(param.flag) !=
|
||
|
|
+ TIMER_FLAG_ONCE ? 1 : 0,
|
||
|
|
+ TIMER_FLAG_MASK_SRC(param.flag) ==
|
||
|
|
+ TIMER_FLAG_EXT_SRC ? 1 : 0,
|
||
|
|
+ TIMER_FLAG_MASK_HANDLE(param.flag) ==
|
||
|
|
+ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
|
||
|
|
+ TIMER_FLAG_NO_HANDLE,
|
||
|
|
+ (unsigned long) param.pid,
|
||
|
|
+ (unsigned long) param.sig);
|
||
|
|
+ if (ret > 0) {
|
||
|
|
+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
|
||
|
|
+ timer, &ret, sizeof(&ret));
|
||
|
|
+ ret = 0;
|
||
|
|
+ }
|
||
|
|
+ break;
|
||
|
|
+ case GPTU_SET_COUNTER:
|
||
|
|
+ lq_set_counter(param.timer, param.flag, param.value, 0, 0);
|
||
|
|
+ if (ret > 0) {
|
||
|
|
+ copy_to_user(&((struct gptu_ioctl_param *) arg)->
|
||
|
|
+ timer, &ret, sizeof(&ret));
|
||
|
|
+ ret = 0;
|
||
|
|
+ }
|
||
|
|
+ break;
|
||
|
|
+ default:
|
||
|
|
+ ret = -ENOTTY;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ return ret;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+static int gptu_open(struct inode *inode, struct file *file)
|
||
|
|
+{
|
||
|
|
+ return 0;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+static int gptu_release(struct inode *inode, struct file *file)
|
||
|
|
+{
|
||
|
|
+ return 0;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+int __init lq_gptu_init(void)
|
||
|
|
+{
|
||
|
|
+ int ret;
|
||
|
|
+ unsigned int i;
|
||
|
|
+
|
||
|
|
+ ltq_w32(0, LQ_GPTU_IRNEN);
|
||
|
|
+ ltq_w32(0xfff, LQ_GPTU_IRNCR);
|
||
|
|
+
|
||
|
|
+ memset(&timer_dev, 0, sizeof(timer_dev));
|
||
|
|
+ mutex_init(&timer_dev.gptu_mutex);
|
||
|
|
+
|
||
|
|
+ lq_enable_gptu();
|
||
|
|
+ timer_dev.number_of_timers = GPTU_ID_CFG * 2;
|
||
|
|
+ lq_disable_gptu();
|
||
|
|
+ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
|
||
|
|
+ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
|
||
|
|
+ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
|
||
|
|
+
|
||
|
|
+ ret = misc_register(&gptu_miscdev);
|
||
|
|
+ if (ret) {
|
||
|
|
+ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
|
||
|
|
+ return ret;
|
||
|
|
+ } else {
|
||
|
|
+ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ for (i = 0; i < timer_dev.number_of_timers; i++) {
|
||
|
|
+ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
|
||
|
|
+ if (ret) {
|
||
|
|
+ for (; i >= 0; i--)
|
||
|
|
+ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
|
||
|
|
+ misc_deregister(&gptu_miscdev);
|
||
|
|
+ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
|
||
|
|
+ return ret;
|
||
|
|
+ } else {
|
||
|
|
+ timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
|
||
|
|
+ disable_irq(timer_dev.timer[i].irq);
|
||
|
|
+ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
|
||
|
|
+ }
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ return 0;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+void __exit lq_gptu_exit(void)
|
||
|
|
+{
|
||
|
|
+ unsigned int i;
|
||
|
|
+
|
||
|
|
+ for (i = 0; i < timer_dev.number_of_timers; i++) {
|
||
|
|
+ if (timer_dev.timer[i].f_irq_on)
|
||
|
|
+ disable_irq(timer_dev.timer[i].irq);
|
||
|
|
+ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
|
||
|
|
+ }
|
||
|
|
+ lq_disable_gptu();
|
||
|
|
+ misc_deregister(&gptu_miscdev);
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+module_init(lq_gptu_init);
|
||
|
|
+module_exit(lq_gptu_exit);
|