mirror of https://github.com/hak5/openwrt.git
312 lines
11 KiB
C
312 lines
11 KiB
C
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/*
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* (C) Copyright 2006
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* Ingenic Semiconductor, <jlwei@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* This file contains the configuration parameters for the pavo board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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//#define DEBUG
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//#define DEBUG_SHELL
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#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
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#define CONFIG_JzRISC 1 /* JzRISC core */
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#define CONFIG_JZSOC 1 /* Jz SoC */
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#define CONFIG_JZ4740 1 /* Jz4740 SoC */
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#define CONFIG_PAVO 1 /* PAVO validation board */
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#define CONFIG_BOARD_NAME "n516"
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#define CONFIG_BOARD_HWREV "1.0"
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#define CONFIG_FIRMWARE_EPOCH "0"
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#define CONFIG_UPDATE_TMPBUF 0x80600000
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#define CONFIG_UPDATE_CHUNKSIZE 0x800000
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#define CONFIG_UPDATE_FILENAME "update.oifw"
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#define CONFIG_UPDATE_FILEEXT ".oifw"
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#define CONFIG_UBI_PARTITION "UBI"
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#define CONFIG_SKIP_LOWLEVEL_INIT 1
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#undef CONFIG_SKIP_RELOCATE_UBOOT
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#if 0
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#define CONFIG_LCD /* LCD support */
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#define CONFIG_JZLCD_METRONOME_800x600
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#define LCD_BPP LCD_COLOR8
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#define WFM_DATA_SIZE ( 1 << 14 )
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#define CONFIG_METRONOME_WF_LEN (64 * (1 << 10))
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#define CONFIG_METRONOME_WF_NAND_OFFSET (0x100000)
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#define BMP_LOGO_HEIGHT 0
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#define CONFIG_UBI_WF_VOLUME "waveforms"
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#define CONFIG_UBI_BOOTSPLASH_VOLUME "bootsplash"
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#define CONFIG_METRONOME_BOOTSPLASH_LEN 480000
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#endif
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#if 0
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#define CONFIG_JZSOC_I2C
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#define CONFIG_HARD_I2C
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 0
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#define CONFIG_LPC_I2C_ADDR 0x54
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#endif
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#define JZ4740_NORBOOT_CFG JZ4740_NORBOOT_16BIT /* NOR Boot config code */
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#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 /* NAND Boot config code */
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#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
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#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
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#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL/256) /* incrementer freq */
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#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */
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#define CONFIG_BAUDRATE 57600
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_MMC 1
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#define CONFIG_GENERIC_MMC 1
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#define CONFIG_JZ_MMC 1
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#define CONFIG_FAT 1
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 ">"
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#define CONFIG_CMDLINE_EDITING
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_BDI /* bdinfo */
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_ECHO /* echo arguments */
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#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
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#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
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#undef CONFIG_CMD_IMI /* iminfo */
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#undef CONFIG_CMD_ITEST /* Integer (and string) test */
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#undef CONFIG_CMD_LOADB /* loadb */
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#undef CONFIG_CMD_LOADS /* loads */
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#undef CONFIG_CMD_NFS /* NFS support */
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#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
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#undef CONFIG_CMD_SOURCE /* "source" command support */
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#undef CONFIG_CMD_XIMG /* Load part of Multi Image */
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#undef CONFIG_CMD_NET
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//#define CONFIG_CMD_ASKENV
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//#define CONFIG_CMD_DHCP
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//#define CONFIG_CMD_PING
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_FAT
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/*#define CONFIG_CMD_UBI*/
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/*#define CONFIG_CMD_MTDPARTS*/
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//#define CONFIG_CMD_JFFS2
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//#define CONFIG_JFFS2_NAND
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//#define CONFIG_JFFS2_CMDLINE
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#define CONFIG_CMD_UPDATE
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#define CONFIG_DOS_PARTITION
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/*#define CONFIG_MTD_PARTITIONS*/
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#define CONFIG_RBTREE
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#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAUL )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#if 0
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#define CONFIG_BOOTDELAY 0
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#define CONFIG_BOOTFILE uImage /* file to load */
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#define CONFIG_BOOTARGS "mem=64M console=ttyS0,57600n8 ip=off rootfstype=ubifs root=ubi:rootfs ubi.mtd=UBI rw panic=5 " MTDPARTS_DEFAULT
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#define CONFIG_BOOTCOMMAND "check_and_update; setenv bootargs $bootargs $batt_level_param; ubi read 0x80600000 bootsplash && show_image 0x80600000; ubi read 0x80600000 kernel; bootm 0x80600000; ubi read 0x80600000 errorsplash && show_image 0x80600000; while test 0 = 0; do check_and_update; done"
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#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
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#define CONFIG_IPADDR 192.168.111.1
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#define CONFIG_SERVERIP 192.168.111.2
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#define MTDIDS_DEFAULT "nand0=jz4740-nand"
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#define MTDPARTS_DEFAULT "mtdparts=jz4740-nand:1M@0(uboot)ro,-@1M(UBI)"
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#define CONFIG_EXTRA_ENV_SETTINGS "mtdids=nand0=jz4740-nand\0mtdparts=mtdparts=jz4740-nand:1M@0(uboot)ro,-@1M(UBI)\0" \
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"stdout=serial\0stderr=lcd\0"
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#endif
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
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#define CONFIG_BOOTDELAY 0
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#define CONFIG_BOOTFILE "uImage" /* file to load */
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#define CONFIG_BOOTARGS "mem=64M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
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#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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/*
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* Serial download configuration
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*
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*/
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "n516 # " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
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#define CONFIG_SYS_MALLOC_LEN 1024*1024*2
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#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
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#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
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#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
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#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
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#define CONFIG_SYS_MEMTEST_START 0x80100000
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#define CONFIG_SYS_MEMTEST_END 0x80800000
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#else
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#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
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#endif
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/*-----------------------------------------------------------------------
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* NAND FLASH configuration
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*/
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_NAND_BASE 0xB8000000
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#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
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/*
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* IPL (Initial Program Loader, integrated inside CPU)
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* Will load first 8k from NAND (SPL) into cache and execute it from there.
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*
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* SPL (Secondary Program Loader)
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* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
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* has to fit into 8kByte. It sets up the CPU and configures the SDRAM
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* controller and the NAND controller so that the special U-Boot image can be
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* loaded from NAND to SDRAM.
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*
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* NUB (NAND U-Boot)
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* This NAND U-Boot (NUB) is a special U-Boot version which can be started
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* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
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*
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*/
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
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/*
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* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
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*/
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
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#define CONFIG_SYS_NAND_BADBLOCK_PAGE 63 /* NAND bad block was marked at this page in a block, starting from 0 */
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#define CONFIG_SYS_NAND_ECC_POS 6
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#ifdef CONFIG_ENV_IS_IN_NAND
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//#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_SIZE (128 * 1024)
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//#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE) /* environment starts here */
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#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
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//#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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#endif
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/*-----------------------------------------------------------------------
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* NOR FLASH and environment organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
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#define PHYS_FLASH_1 0xa8000000 /* Flash Bank #1 */
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/* The following #defines are needed to get flash environment right */
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* in pavo/config.mk TEXT_BASE=0x88000000*/
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#define CONFIG_SYS_SYS_MONITOR_BASE TEXT_BASE /* in pavo/config.mk TEXT_BASE=0x88000000*/
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#define CONFIG_SYS_MONITOR_LEN (256*1024) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_IS_NOWHERE 1
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#define CONFIG_ENV_ADDR 0xa8040000
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#define CONFIG_ENV_SIZE 0x20000
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#endif
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/*-----------------------------------------------------------------------
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* SDRAM Info.
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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// SDRAM paramters
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#define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */
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#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
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#define SDRAM_ROW 13 /* Row address: 11 to 13 */
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#define SDRAM_COL 9 /* Column address: 8 to 12 */
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#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
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// SDRAM Timings, unit: ns
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#define SDRAM_TRAS 45 /* RAS# Active Time */
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#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
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#define SDRAM_TPC 20 /* RAS# Precharge Time */
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#define SDRAM_TRWL 7 /* Write Latency Time */
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#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_DCACHE_SIZE 16384
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#define CONFIG_SYS_ICACHE_SIZE 16384
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#define CONFIG_SYS_CACHELINE_SIZE 32
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/*-----------------------------------------------------------------------
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* GPIO definition
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*/
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#define GPIO_SD_VCC_EN_N 113 /* GPD17 */
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#define GPIO_SD_CD_N 103 /* GPD7 */
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#define GPIO_SD_WP 111 /* GPD15 */
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#define GPIO_USB_DETE 115 /* GPD6 */
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//#define GPIO_DC_DETE_N 103 /* GPD7 */
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#define GPIO_CHARG_STAT_N 112 /* GPD15 */
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#define GPIO_DISP_OFF_N 97 /* GPD1 */
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#define GPIO_UDC_HOTPLUG 100 /* GPD4 */
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#define GPIO_LED_EN 124 /* GPD28 */
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#define GPIO_RST_L 50 /* GPB18 LCD_SPL */
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#define GPIO_LCDRDY 49 /* GPB17 LCD_CLS */
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#define GPIO_STBY 86 /* GPC22 LCD_PS */
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#define GPIO_ERR 87 /* GPC23 LCD_REV */
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#endif /* __CONFIG_H */
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