mirror of https://github.com/hak5/openwrt.git
250 lines
7.5 KiB
C
250 lines
7.5 KiB
C
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/******************************************************************************
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**
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** FILE NAME : ifxmips_atm_core.h
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** PROJECT : UEIP
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** MODULES : ATM
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**
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** DATE : 7 Jul 2009
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** AUTHOR : Xu Liang
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** DESCRIPTION : ATM driver header file (core functions)
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** COPYRIGHT : Copyright (c) 2006
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** Infineon Technologies AG
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** Am Campeon 1-12, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** HISTORY
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** $Date $Author $Comment
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** 17 JUN 2009 Xu Liang Init Version
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*******************************************************************************/
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#ifndef IFXMIPS_ATM_CORE_H
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#define IFXMIPS_ATM_CORE_H
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#include "ifxmips_compat.h"
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#include "ifx_atm.h"
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#include "ifxmips_atm_ppe_common.h"
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#include "ifxmips_atm_fw_regs_common.h"
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/*
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* ####################################
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* Definition
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* ####################################
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*/
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/*
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* Compile Options
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*/
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#define ENABLE_DEBUG 1
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#define ENABLE_ASSERT 1
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#define INLINE
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#define DEBUG_DUMP_SKB 1
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#define DEBUG_QOS 1
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#define ENABLE_DBG_PROC 1
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#define ENABLE_FW_PROC 1
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#ifdef CONFIG_IFX_ATM_TASKLET
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#define ENABLE_TASKLET 1
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#endif
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/*
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* Debug/Assert/Error Message
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*/
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#define DBG_ENABLE_MASK_ERR (1 << 0)
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#define DBG_ENABLE_MASK_DEBUG_PRINT (1 << 1)
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#define DBG_ENABLE_MASK_ASSERT (1 << 2)
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#define DBG_ENABLE_MASK_DUMP_SKB_RX (1 << 8)
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#define DBG_ENABLE_MASK_DUMP_SKB_TX (1 << 9)
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#define DBG_ENABLE_MASK_DUMP_QOS (1 << 10)
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#define DBG_ENABLE_MASK_DUMP_INIT (1 << 11)
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#define DBG_ENABLE_MASK_ALL (DBG_ENABLE_MASK_ERR | DBG_ENABLE_MASK_DEBUG_PRINT | DBG_ENABLE_MASK_ASSERT | DBG_ENABLE_MASK_DUMP_SKB_RX | DBG_ENABLE_MASK_DUMP_SKB_TX | DBG_ENABLE_MASK_DUMP_QOS | DBG_ENABLE_MASK_DUMP_INIT)
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#define err(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ERR) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
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#if defined(ENABLE_DEBUG) && ENABLE_DEBUG
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#undef dbg
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#define dbg(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT) ) printk(KERN_WARNING __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
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#else
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#if !defined(dbg)
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#define dbg(format, arg...)
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#endif
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#endif
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#if defined(ENABLE_ASSERT) && ENABLE_ASSERT
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#define ASSERT(cond, format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ASSERT) && !(cond) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
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#else
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#define ASSERT(cond, format, arg...)
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#endif
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/*
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* Constants
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*/
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#define DEFAULT_TX_LINK_RATE 3200 // in cells
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/*
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* ATM Port, QSB Queue, DMA RX/TX Channel Parameters
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*/
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#define ATM_PORT_NUMBER 2
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#define MAX_QUEUE_NUMBER 16
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#define OAM_RX_QUEUE 15
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#define QSB_RESERVE_TX_QUEUE 0
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#define FIRST_QSB_QID 1
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#define MAX_PVC_NUMBER (MAX_QUEUE_NUMBER - FIRST_QSB_QID)
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#define MAX_RX_DMA_CHANNEL_NUMBER 8
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#define MAX_TX_DMA_CHANNEL_NUMBER 16
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#define DATA_BUFFER_ALIGNMENT EMA_ALIGNMENT
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#define DESC_ALIGNMENT 8
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#define DEFAULT_RX_HUNT_BITTH 4
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/*
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* RX DMA Channel Allocation
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*/
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#define RX_DMA_CH_OAM 0
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#define RX_DMA_CH_AAL 1
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#define RX_DMA_CH_TOTAL 2
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#define RX_DMA_CH_OAM_DESC_LEN 32
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#define RX_DMA_CH_OAM_BUF_SIZE (CELL_SIZE & ~15)
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#define RX_DMA_CH_AAL_BUF_SIZE (2048 - 48)
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/*
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* OAM Constants
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*/
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#define OAM_HTU_ENTRY_NUMBER 3
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#define OAM_F4_SEG_HTU_ENTRY 0
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#define OAM_F4_TOT_HTU_ENTRY 1
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#define OAM_F5_HTU_ENTRY 2
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#define OAM_F4_CELL_ID 0
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#define OAM_F5_CELL_ID 15
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//#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
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// #undef OAM_HTU_ENTRY_NUMBER
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// #define OAM_HTU_ENTRY_NUMBER 4
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// #define OAM_ARQ_HTU_ENTRY 3
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//#endif
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/*
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* RX Frame Definitions
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*/
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#define MAX_RX_PACKET_ALIGN_BYTES 3
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#define MAX_RX_PACKET_PADDING_BYTES 3
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#define RX_INBAND_TRAILER_LENGTH 8
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#define MAX_RX_FRAME_EXTRA_BYTES (RX_INBAND_TRAILER_LENGTH + MAX_RX_PACKET_ALIGN_BYTES + MAX_RX_PACKET_PADDING_BYTES)
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/*
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* TX Frame Definitions
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*/
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#define MAX_TX_HEADER_ALIGN_BYTES 12
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#define MAX_TX_PACKET_ALIGN_BYTES 3
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#define MAX_TX_PACKET_PADDING_BYTES 3
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#define TX_INBAND_HEADER_LENGTH 8
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#define MAX_TX_FRAME_EXTRA_BYTES (TX_INBAND_HEADER_LENGTH + MAX_TX_HEADER_ALIGN_BYTES + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES)
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/*
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* Cell Constant
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*/
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#define CELL_SIZE ATM_AAL0_SDU
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/*
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* ####################################
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* Data Type
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* ####################################
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*/
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typedef struct {
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unsigned int h;
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unsigned int l;
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} ppe_u64_t;
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struct port {
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unsigned int tx_max_cell_rate;
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unsigned int tx_current_cell_rate;
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struct atm_dev *dev;
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};
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struct connection {
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struct atm_vcc *vcc;
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volatile struct tx_descriptor
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*tx_desc;
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unsigned int tx_desc_pos;
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struct sk_buff **tx_skb;
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unsigned int aal5_vcc_crc_err; /* number of packets with CRC error */
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unsigned int aal5_vcc_oversize_sdu; /* number of packets with oversize error */
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unsigned int port;
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};
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struct atm_priv_data {
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unsigned long conn_table;
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struct connection conn[MAX_PVC_NUMBER];
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volatile struct rx_descriptor
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*aal_desc;
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unsigned int aal_desc_pos;
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volatile struct rx_descriptor
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*oam_desc;
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unsigned char *oam_buf;
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unsigned int oam_desc_pos;
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struct port port[ATM_PORT_NUMBER];
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unsigned int wrx_pdu; /* successfully received AAL5 packet */
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unsigned int wrx_drop_pdu; /* AAL5 packet dropped by driver on RX */
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unsigned int wtx_pdu; /* successfully tranmitted AAL5 packet */
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unsigned int wtx_err_pdu; /* error AAL5 packet */
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unsigned int wtx_drop_pdu; /* AAL5 packet dropped by driver on TX */
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ppe_u64_t wrx_total_byte;
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ppe_u64_t wtx_total_byte;
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unsigned int prev_wrx_total_byte;
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unsigned int prev_wtx_total_byte;
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void *aal_desc_base;
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void *oam_desc_base;
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void *oam_buf_base;
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void *tx_desc_base;
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void *tx_skb_base;
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};
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/*
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* ####################################
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* Declaration
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* ####################################
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*/
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extern unsigned int ifx_atm_dbg_enable;
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extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor);
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extern void ifx_atm_init_chip(void);
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extern void ifx_atm_uninit_chip(void);
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extern int ifx_pp32_start(int pp32);
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extern void ifx_pp32_stop(int pp32);
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#endif // IFXMIPS_ATM_CORE_H
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