mirror of https://github.com/hak5/openwrt.git
277 lines
8.2 KiB
C
277 lines
8.2 KiB
C
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/*
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<:copyright-gpl
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Copyright 2002 Broadcom Corp. All Rights Reserved.
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This program is free software; you can distribute it and/or modify it
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under the terms of the GNU General Public License (Version 2) as
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published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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:>
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/addrspace.h>
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#include <bcm_intr.h>
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#include <bcm_map_part.h>
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#include <bcmpci.h>
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#include <linux/delay.h>
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#if defined(CONFIG_USB)
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#if 0
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#define DPRINT(x...) printk(x)
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#else
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#define DPRINT(x...)
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#endif
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static int
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pci63xx_int_read(unsigned int devfn, int where, u32 * value, int size);
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static int
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pci63xx_int_write(unsigned int devfn, int where, u32 * value, int size);
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static bool usb_mem_size_rd = FALSE;
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static uint32 usb_mem_base = 0;
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static uint32 usb_cfg_space_cmd_reg = 0;
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#endif
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static bool pci_mem_size_rd = FALSE;
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static volatile MpiRegisters * mpi = (MpiRegisters *)(MPI_BASE);
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static void mpi_SetupPciConfigAccess(uint32 addr)
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{
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mpi->l2pcfgctl = (DIR_CFG_SEL | DIR_CFG_USEREG | addr) & ~CONFIG_TYPE;
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}
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static void mpi_ClearPciConfigAccess(void)
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{
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mpi->l2pcfgctl = 0x00000000;
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}
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#if defined(CONFIG_USB)
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/* --------------------------------------------------------------------------
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Name: pci63xx_int_write
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Abstract: PCI Config write on internal device(s)
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-------------------------------------------------------------------------- */
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static int
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pci63xx_int_write(unsigned int devfn, int where, u32 * value, int size)
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{
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if (PCI_SLOT(devfn) != USB_HOST_SLOT) {
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return PCIBIOS_SUCCESSFUL;
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}
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switch (size) {
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case 1:
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DPRINT("W => Slot: %d Where: %2X Len: %d Data: %02X\n",
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PCI_SLOT(devfn), where, size, *value);
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break;
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case 2:
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DPRINT("W => Slot: %d Where: %2X Len: %d Data: %04X\n",
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PCI_SLOT(devfn), where, size, *value);
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switch (where) {
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case PCI_COMMAND:
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usb_cfg_space_cmd_reg = *value;
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break;
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default:
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break;
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}
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break;
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case 4:
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DPRINT("W => Slot: %d Where: %2X Len: %d Data: %08lX\n",
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PCI_SLOT(devfn), where, size, *value);
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switch (where) {
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case PCI_BASE_ADDRESS_0:
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if (*value == 0xffffffff) {
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usb_mem_size_rd = TRUE;
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} else {
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usb_mem_base = *value;
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}
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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/* --------------------------------------------------------------------------
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Name: pci63xx_int_read
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Abstract: PCI Config read on internal device(s)
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-------------------------------------------------------------------------- */
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static int
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pci63xx_int_read(unsigned int devfn, int where, u32 * value, int size)
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{
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uint32 retValue = 0xFFFFFFFF;
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if (PCI_SLOT(devfn) != USB_HOST_SLOT) {
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return PCIBIOS_SUCCESSFUL;
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}
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// For now, this is specific to the USB Host controller. We can
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// make it more general if we have to...
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// Emulate PCI Config accesses
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switch (where) {
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case PCI_VENDOR_ID:
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case PCI_DEVICE_ID:
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retValue = PCI_VENDOR_ID_BROADCOM | 0x63000000;
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break;
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case PCI_COMMAND:
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case PCI_STATUS:
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retValue = (0x0006 << 16) | usb_cfg_space_cmd_reg;
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break;
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case PCI_CLASS_REVISION:
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case PCI_CLASS_DEVICE:
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retValue = (PCI_CLASS_SERIAL_USB << 16) | (0x10 << 8) | 0x01;
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break;
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case PCI_BASE_ADDRESS_0:
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if (usb_mem_size_rd) {
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retValue = USB_BAR0_MEM_SIZE;
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} else {
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if (usb_mem_base != 0)
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retValue = usb_mem_base;
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else
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retValue = USB_HOST_BASE;
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}
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usb_mem_size_rd = FALSE;
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break;
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case PCI_CACHE_LINE_SIZE:
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case PCI_LATENCY_TIMER:
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retValue = 0;
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break;
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case PCI_HEADER_TYPE:
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retValue = PCI_HEADER_TYPE_NORMAL;
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break;
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case PCI_SUBSYSTEM_VENDOR_ID:
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retValue = PCI_VENDOR_ID_BROADCOM;
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break;
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case PCI_SUBSYSTEM_ID:
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retValue = 0x6300;
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break;
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case PCI_INTERRUPT_LINE:
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retValue = INTERRUPT_ID_USBH;
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break;
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default:
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break;
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}
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switch (size) {
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case 1:
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*value = (retValue >> ((where & 3) << 3)) & 0xff;
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DPRINT("R <= Slot: %d Where: %2X Len: %d Data: %02X\n",
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PCI_SLOT(devfn), where, size, *value);
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break;
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case 2:
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*value = (retValue >> ((where & 3) << 3)) & 0xffff;
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DPRINT("R <= Slot: %d Where: %2X Len: %d Data: %04X\n",
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PCI_SLOT(devfn), where, size, *value);
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break;
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case 4:
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*value = retValue;
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DPRINT("R <= Slot: %d Where: %2X Len: %d Data: %08lX\n",
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PCI_SLOT(devfn), where, size, *value);
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break;
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default:
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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#endif
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static int bcm96348_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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volatile unsigned char *ioBase = (unsigned char *)(mpi->l2piobase | KSEG1);
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uint32 data;
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#if defined(CONFIG_USB)
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if (PCI_SLOT(devfn) == USB_HOST_SLOT)
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return pci63xx_int_read(devfn, where, val, size);
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#endif
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mpi_SetupPciConfigAccess(BCM_PCI_CFG(PCI_SLOT(devfn), PCI_FUNC(devfn), where));
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data = *(uint32 *)ioBase;
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switch(size) {
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case 1:
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*val = (data >> ((where & 3) << 3)) & 0xff;
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break;
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case 2:
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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break;
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case 4:
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*val = data;
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/* Special case for reading PCI device range */
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if ((where >= PCI_BASE_ADDRESS_0) && (where <= PCI_BASE_ADDRESS_5)) {
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if (pci_mem_size_rd) {
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/* bcm6348 PCI memory window minimum size is 64K */
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*val &= PCI_SIZE_64K;
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}
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}
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break;
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default:
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break;
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}
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pci_mem_size_rd = FALSE;
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mpi_ClearPciConfigAccess();
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return PCIBIOS_SUCCESSFUL;
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}
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static int bcm96348_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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volatile unsigned char *ioBase = (unsigned char *)(mpi->l2piobase | KSEG1);
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uint32 data;
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#if defined(CONFIG_USB)
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if (PCI_SLOT(devfn) == USB_HOST_SLOT)
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return pci63xx_int_write(devfn, where, &val, size);
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#endif
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mpi_SetupPciConfigAccess(BCM_PCI_CFG(PCI_SLOT(devfn), PCI_FUNC(devfn), where));
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data = *(uint32 *)ioBase;
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switch(size) {
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case 1:
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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break;
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case 2:
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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break;
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case 4:
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data = val;
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/* Special case for reading PCI device range */
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if ((where >= PCI_BASE_ADDRESS_0) && (where <= PCI_BASE_ADDRESS_5)) {
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if (val == 0xffffffff)
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pci_mem_size_rd = TRUE;
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}
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break;
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default:
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break;
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}
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*(uint32 *)ioBase = data;
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udelay(500);
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mpi_ClearPciConfigAccess();
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops bcm96348_pci_ops = {
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.read = bcm96348_pcibios_read,
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.write = bcm96348_pcibios_write
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};
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