mirror of https://github.com/hak5/openwrt-owl.git
295 lines
8.5 KiB
Diff
295 lines
8.5 KiB
Diff
--- a/arch/mips/ar231x/Makefile
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+++ b/arch/mips/ar231x/Makefile
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@@ -14,3 +14,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
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obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
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obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
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+obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
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--- /dev/null
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+++ b/arch/mips/ar231x/pci.c
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@@ -0,0 +1,230 @@
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+/*
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * as published by the Free Software Foundation; either version 2
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+ * of the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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+ */
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+
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+#include <linux/types.h>
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+#include <linux/pci.h>
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/mm.h>
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+#include <linux/spinlock.h>
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+#include <linux/delay.h>
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+#include <linux/irq.h>
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+#include <asm/bootinfo.h>
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+#include <asm/paccess.h>
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+#include <asm/irq_cpu.h>
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+#include <asm/io.h>
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+#include <ar231x_platform.h>
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+#include <ar231x.h>
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+#include <ar2315_regs.h>
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+#include "devices.h"
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+
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+#define AR531X_MEM_BASE 0x80800000UL
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+#define AR531X_MEM_SIZE 0x00ffffffUL
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+#define AR531X_IO_SIZE 0x00007fffUL
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+
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+static unsigned long configspace;
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+
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+static int config_access(int devfn, int where, int size, u32 *ptr, bool write)
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+{
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+ unsigned long flags;
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+ int func = PCI_FUNC(devfn);
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+ int dev = PCI_SLOT(devfn);
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+ u32 value = 0;
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+ int err = 0;
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+ u32 addr;
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+
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+ if (((dev != 0) && (dev != 3)) || (func > 2))
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ /* Select Configuration access */
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+ local_irq_save(flags);
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+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
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+ mb();
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+
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+ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where;
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+ if (size == 1)
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+ addr ^= 0x3;
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+ else if (size == 2)
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+ addr ^= 0x2;
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+
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+ if (write) {
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+ value = *ptr;
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+ if (size == 1)
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+ err = put_dbe(value, (u8 *) addr);
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+ else if (size == 2)
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+ err = put_dbe(value, (u16 *) addr);
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+ else if (size == 4)
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+ err = put_dbe(value, (u32 *) addr);
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+ } else {
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+ if (size == 1)
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+ err = get_dbe(value, (u8 *) addr);
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+ else if (size == 2)
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+ err = get_dbe(value, (u16 *) addr);
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+ else if (size == 4)
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+ err = get_dbe(value, (u32 *) addr);
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+ if (err)
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+ *ptr = 0xffffffff;
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+ else
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+ *ptr = value;
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+ }
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+
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+ /* Select Memory access */
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+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
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+ local_irq_restore(flags);
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+
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+ return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL);
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+}
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+
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+static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value)
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+{
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+ return config_access(devfn, where, size, value, 0);
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+}
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+
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+static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
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+{
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+ return config_access(devfn, where, size, &value, 1);
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+}
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+
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+struct pci_ops ar231x_pci_ops = {
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+ .read = ar231x_pci_read,
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+ .write = ar231x_pci_write,
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+};
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+
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+static struct resource ar231x_mem_resource = {
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+ .name = "AR531x PCI MEM",
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+ .start = AR531X_MEM_BASE,
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+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000,
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+static struct resource ar231x_io_resource = {
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+ .name = "AR531x PCI I/O",
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+ .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE,
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+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1,
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+ .flags = IORESOURCE_IO,
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+};
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+
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+struct pci_controller ar231x_pci_controller = {
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+ .pci_ops = &ar231x_pci_ops,
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+ .mem_resource = &ar231x_mem_resource,
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+ .io_resource = &ar231x_io_resource,
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+ .mem_offset = 0x00000000UL,
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+ .io_offset = 0x00000000UL,
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+};
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+
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+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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+{
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+ return AR2315_IRQ_LCBUS_PCI;
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+}
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+
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+int pcibios_plat_dev_init(struct pci_dev *dev)
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+{
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+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
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+ pci_write_config_word(dev, 0x40, 0);
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+
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+ /* Clear any pending Abort or external Interrupts
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+ * and enable interrupt processing */
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+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0);
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+ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
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+ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
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+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE);
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+
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+ return 0;
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+}
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+
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+static void
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+ar2315_pci_fixup(struct pci_dev *dev)
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+{
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+ unsigned int devfn = dev->devfn;
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+
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+ if (dev->bus->number != 0)
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+ return;
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+
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+ /* Only fix up the PCI host settings */
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+ if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0))
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+ return;
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+
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+ /* Fix up MBARs */
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+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
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+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
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+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
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+ pci_write_config_dword(dev, PCI_COMMAND,
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+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
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+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
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+ PCI_COMMAND_FAST_BACK);
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+}
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+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup);
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+
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+static int __init
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+ar2315_pci_init(void)
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+{
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+ u32 reg;
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+
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+ if (ar231x_devtype != DEV_TYPE_AR2315)
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+ return -ENODEV;
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+
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+ configspace = (unsigned long) ioremap_nocache(AR2315_PCIEXT, 1*1024*1024); /* Remap PCI config space */
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+ ar231x_pci_controller.io_map_base =
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+ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE);
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+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */
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+
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+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
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+ msleep(10);
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+
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+ reg &= ~AR2315_RESET_PCIDMA;
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+ ar231x_write_reg(AR2315_RESET, reg);
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+ msleep(10);
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+
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+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
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+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
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+
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+ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
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+ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
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+ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
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+ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
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+ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
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+ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT));
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+
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+ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
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+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
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+ AR2315_PCIRST_LOW);
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+ msleep(100);
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+
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+ /* Bring the PCI out of reset */
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+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
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+ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
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+
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+ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
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+ 0x1E | /* 1GB uncached */
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+ (1 << 5) | /* Enable uncached */
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+ (0x2 << 30) /* Base: 0x80000000 */
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+ );
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+ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
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+
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+ msleep(500);
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+
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+ /* dirty hack - anyone with a datasheet that knows the memory map ? */
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+ ioport_resource.start = 0x10000000;
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+ ioport_resource.end = 0xffffffff;
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+ iomem_resource.start = 0x10000000;
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+ iomem_resource.end = 0xffffffff;
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+
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+ register_pci_controller(&ar231x_pci_controller);
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+
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+ return 0;
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+}
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+
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+arch_initcall(ar2315_pci_init);
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--- a/arch/mips/ar231x/Kconfig
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+++ b/arch/mips/ar231x/Kconfig
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@@ -14,3 +14,10 @@ config ATHEROS_AR2315
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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default y
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+
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+config ATHEROS_AR2315_PCI
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+ bool "PCI support"
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+ depends on ATHEROS_AR2315
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+ select HW_HAS_PCI
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+ select PCI
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+ default y
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--- a/arch/mips/ar231x/ar2315.c
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+++ b/arch/mips/ar231x/ar2315.c
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@@ -64,6 +64,27 @@ static inline void ar2315_gpio_irq(void)
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do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
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}
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+#ifdef CONFIG_ATHEROS_AR2315_PCI
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+static inline void pci_abort_irq(void)
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+{
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+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT);
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+}
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+
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+static inline void pci_ack_irq(void)
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+{
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+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
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+}
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+
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+void ar2315_pci_irq(int irq)
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+{
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+ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
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+ pci_abort_irq();
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+ else {
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+ do_IRQ(irq);
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+ pci_ack_irq();
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+ }
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+}
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+#endif /* CONFIG_ATHEROS_AR2315_PCI */
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/*
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* Called when an interrupt is received, this function
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@@ -82,6 +103,10 @@ ar2315_irq_dispatch(void)
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do_IRQ(AR2315_IRQ_WLAN0_INTRS);
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else if (pending & CAUSEF_IP4)
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do_IRQ(AR2315_IRQ_ENET0_INTRS);
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+#ifdef CONFIG_ATHEROS_AR2315_PCI
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+ else if (pending & CAUSEF_IP5)
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+ ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI);
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+#endif
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else if (pending & CAUSEF_IP2) {
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unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
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