mirror of https://github.com/hak5/openwrt-owl.git
955 lines
23 KiB
Diff
955 lines
23 KiB
Diff
From f851b4ea6cae9fd5875036b6d3968375882ce56b Mon Sep 17 00:00:00 2001
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From: James Liao <jamesjj.liao@mediatek.com>
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Date: Thu, 23 Apr 2015 10:35:39 +0200
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Subject: [PATCH 02/76] clk: mediatek: Add initial common clock support for
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Mediatek SoCs.
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This patch adds common clock support for Mediatek SoCs, including plls,
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muxes and clock gates.
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Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
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Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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---
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drivers/clk/Makefile | 1 +
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drivers/clk/mediatek/Makefile | 1 +
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drivers/clk/mediatek/clk-gate.c | 137 ++++++++++++++++
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drivers/clk/mediatek/clk-gate.h | 49 ++++++
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drivers/clk/mediatek/clk-mtk.c | 220 ++++++++++++++++++++++++++
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drivers/clk/mediatek/clk-mtk.h | 159 +++++++++++++++++++
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drivers/clk/mediatek/clk-pll.c | 332 +++++++++++++++++++++++++++++++++++++++
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7 files changed, 899 insertions(+)
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create mode 100644 drivers/clk/mediatek/Makefile
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create mode 100644 drivers/clk/mediatek/clk-gate.c
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create mode 100644 drivers/clk/mediatek/clk-gate.h
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create mode 100644 drivers/clk/mediatek/clk-mtk.c
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create mode 100644 drivers/clk/mediatek/clk-mtk.h
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create mode 100644 drivers/clk/mediatek/clk-pll.c
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--- a/drivers/clk/Makefile
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+++ b/drivers/clk/Makefile
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@@ -51,6 +51,7 @@ obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
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obj-$(CONFIG_ARCH_HIP04) += hisilicon/
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obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
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obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
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+obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
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ifeq ($(CONFIG_COMMON_CLK), y)
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obj-$(CONFIG_ARCH_MMP) += mmp/
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endif
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--- /dev/null
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+++ b/drivers/clk/mediatek/Makefile
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@@ -0,0 +1 @@
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+obj-y += clk-mtk.o clk-pll.o clk-gate.o
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--- /dev/null
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+++ b/drivers/clk/mediatek/clk-gate.c
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@@ -0,0 +1,137 @@
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+/*
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+ * Copyright (c) 2014 MediaTek Inc.
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+ * Author: James Liao <jamesjj.liao@mediatek.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+
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+#include <linux/io.h>
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+#include <linux/slab.h>
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+#include <linux/delay.h>
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+#include <linux/clkdev.h>
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+
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+#include "clk-mtk.h"
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+#include "clk-gate.h"
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+
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+static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
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+{
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+ struct mtk_clk_gate *cg = to_clk_gate(hw);
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+ u32 val;
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+
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+ regmap_read(cg->regmap, cg->sta_ofs, &val);
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+
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+ val &= BIT(cg->bit);
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+
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+ return val == 0;
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+}
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+
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+static int mtk_cg_bit_is_set(struct clk_hw *hw)
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+{
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+ struct mtk_clk_gate *cg = to_clk_gate(hw);
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+ u32 val;
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+
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+ regmap_read(cg->regmap, cg->sta_ofs, &val);
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+
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+ val &= BIT(cg->bit);
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+
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+ return val != 0;
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+}
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+
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+static void mtk_cg_set_bit(struct clk_hw *hw)
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+{
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+ struct mtk_clk_gate *cg = to_clk_gate(hw);
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+
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+ regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
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+}
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+
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+static void mtk_cg_clr_bit(struct clk_hw *hw)
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+{
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+ struct mtk_clk_gate *cg = to_clk_gate(hw);
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+
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+ regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
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+}
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+
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+static int mtk_cg_enable(struct clk_hw *hw)
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+{
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+ mtk_cg_clr_bit(hw);
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+
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+ return 0;
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+}
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+
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+static void mtk_cg_disable(struct clk_hw *hw)
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+{
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+ mtk_cg_set_bit(hw);
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+}
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+
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+static int mtk_cg_enable_inv(struct clk_hw *hw)
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+{
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+ mtk_cg_set_bit(hw);
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+
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+ return 0;
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+}
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+
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+static void mtk_cg_disable_inv(struct clk_hw *hw)
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+{
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+ mtk_cg_clr_bit(hw);
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+}
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+
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+const struct clk_ops mtk_clk_gate_ops_setclr = {
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+ .is_enabled = mtk_cg_bit_is_cleared,
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+ .enable = mtk_cg_enable,
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+ .disable = mtk_cg_disable,
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+};
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+
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+const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
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+ .is_enabled = mtk_cg_bit_is_set,
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+ .enable = mtk_cg_enable_inv,
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+ .disable = mtk_cg_disable_inv,
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+};
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+
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+struct clk *mtk_clk_register_gate(
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+ const char *name,
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+ const char *parent_name,
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+ struct regmap *regmap,
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+ int set_ofs,
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+ int clr_ofs,
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+ int sta_ofs,
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+ u8 bit,
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+ const struct clk_ops *ops)
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+{
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+ struct mtk_clk_gate *cg;
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+ struct clk *clk;
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+ struct clk_init_data init;
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+
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+ cg = kzalloc(sizeof(*cg), GFP_KERNEL);
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+ if (!cg)
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+ return ERR_PTR(-ENOMEM);
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+
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+ init.name = name;
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+ init.flags = CLK_SET_RATE_PARENT;
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+ init.parent_names = parent_name ? &parent_name : NULL;
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+ init.num_parents = parent_name ? 1 : 0;
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+ init.ops = ops;
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+
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+ cg->regmap = regmap;
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+ cg->set_ofs = set_ofs;
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+ cg->clr_ofs = clr_ofs;
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+ cg->sta_ofs = sta_ofs;
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+ cg->bit = bit;
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+
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+ cg->hw.init = &init;
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+
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+ clk = clk_register(NULL, &cg->hw);
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+ if (IS_ERR(clk))
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+ kfree(cg);
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+
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+ return clk;
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+}
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--- /dev/null
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+++ b/drivers/clk/mediatek/clk-gate.h
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@@ -0,0 +1,49 @@
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+/*
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+ * Copyright (c) 2014 MediaTek Inc.
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+ * Author: James Liao <jamesjj.liao@mediatek.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#ifndef __DRV_CLK_GATE_H
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+#define __DRV_CLK_GATE_H
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+
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+#include <linux/regmap.h>
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+#include <linux/clk.h>
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+#include <linux/clk-provider.h>
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+
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+struct mtk_clk_gate {
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+ struct clk_hw hw;
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+ struct regmap *regmap;
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+ int set_ofs;
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+ int clr_ofs;
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+ int sta_ofs;
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+ u8 bit;
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+};
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+
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+static inline struct mtk_clk_gate *to_clk_gate(struct clk_hw *hw)
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+{
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+ return container_of(hw, struct mtk_clk_gate, hw);
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+}
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+
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+extern const struct clk_ops mtk_clk_gate_ops_setclr;
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+extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
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+
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+struct clk *mtk_clk_register_gate(
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+ const char *name,
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+ const char *parent_name,
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+ struct regmap *regmap,
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+ int set_ofs,
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+ int clr_ofs,
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+ int sta_ofs,
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+ u8 bit,
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+ const struct clk_ops *ops);
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+
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+#endif /* __DRV_CLK_GATE_H */
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--- /dev/null
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+++ b/drivers/clk/mediatek/clk-mtk.c
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@@ -0,0 +1,220 @@
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+/*
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+ * Copyright (c) 2014 MediaTek Inc.
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+ * Author: James Liao <jamesjj.liao@mediatek.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/slab.h>
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+#include <linux/delay.h>
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+#include <linux/clkdev.h>
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+#include <linux/mfd/syscon.h>
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+
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+#include "clk-mtk.h"
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+#include "clk-gate.h"
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+
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+struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
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+{
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+ int i;
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+ struct clk_onecell_data *clk_data;
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+
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+ clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
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+ if (!clk_data)
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+ return NULL;
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+
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+ clk_data->clks = kcalloc(clk_num, sizeof(*clk_data->clks), GFP_KERNEL);
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+ if (!clk_data->clks)
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+ goto err_out;
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+
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+ clk_data->clk_num = clk_num;
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+
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+ for (i = 0; i < clk_num; i++)
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+ clk_data->clks[i] = ERR_PTR(-ENOENT);
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+
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+ return clk_data;
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+err_out:
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+ kfree(clk_data);
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+
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+ return NULL;
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+}
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+
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+void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
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+ struct clk_onecell_data *clk_data)
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+{
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+ int i;
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+ struct clk *clk;
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+
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+ for (i = 0; i < num; i++) {
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+ const struct mtk_fixed_factor *ff = &clks[i];
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+
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+ clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name,
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+ CLK_SET_RATE_PARENT, ff->mult, ff->div);
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+
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+ if (IS_ERR(clk)) {
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+ pr_err("Failed to register clk %s: %ld\n",
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+ ff->name, PTR_ERR(clk));
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+ continue;
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+ }
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+
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+ if (clk_data)
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+ clk_data->clks[ff->id] = clk;
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+ }
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+}
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+
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+int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
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+ int num, struct clk_onecell_data *clk_data)
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+{
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+ int i;
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+ struct clk *clk;
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+ struct regmap *regmap;
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+
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+ if (!clk_data)
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+ return -ENOMEM;
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+
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+ regmap = syscon_node_to_regmap(node);
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+ if (IS_ERR(regmap)) {
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+ pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
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+ PTR_ERR(regmap));
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+ return PTR_ERR(regmap);
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+ }
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+
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+ for (i = 0; i < num; i++) {
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+ const struct mtk_gate *gate = &clks[i];
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+
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+ clk = mtk_clk_register_gate(gate->name, gate->parent_name,
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+ regmap,
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+ gate->regs->set_ofs,
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+ gate->regs->clr_ofs,
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+ gate->regs->sta_ofs,
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+ gate->shift, gate->ops);
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+
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+ if (IS_ERR(clk)) {
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+ pr_err("Failed to register clk %s: %ld\n",
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+ gate->name, PTR_ERR(clk));
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+ continue;
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+ }
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+
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+ clk_data->clks[gate->id] = clk;
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+ }
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+
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+ return 0;
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+}
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+
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+struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
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+ void __iomem *base, spinlock_t *lock)
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+{
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+ struct clk *clk;
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+ struct clk_mux *mux = NULL;
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+ struct clk_gate *gate = NULL;
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+ struct clk_divider *div = NULL;
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+ struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL;
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+ const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *div_ops = NULL;
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+ const char * const *parent_names;
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+ const char *parent;
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+ int num_parents;
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+ int ret;
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+
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+ if (mc->mux_shift >= 0) {
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+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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+ if (!mux)
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+ return ERR_PTR(-ENOMEM);
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+
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+ mux->reg = base + mc->mux_reg;
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+ mux->mask = BIT(mc->mux_width) - 1;
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+ mux->shift = mc->mux_shift;
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+ mux->lock = lock;
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+
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+ mux_hw = &mux->hw;
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+ mux_ops = &clk_mux_ops;
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+
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+ parent_names = mc->parent_names;
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+ num_parents = mc->num_parents;
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+ } else {
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+ parent = mc->parent;
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+ parent_names = &parent;
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+ num_parents = 1;
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+ }
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+
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+ if (mc->gate_shift >= 0) {
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+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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+ if (!gate) {
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+ ret = -ENOMEM;
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+ goto err_out;
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+ }
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+
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+ gate->reg = base + mc->gate_reg;
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+ gate->bit_idx = mc->gate_shift;
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+ gate->flags = CLK_GATE_SET_TO_DISABLE;
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+ gate->lock = lock;
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+
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+ gate_hw = &gate->hw;
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+ gate_ops = &clk_gate_ops;
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+ }
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+
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+ if (mc->divider_shift >= 0) {
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+ div = kzalloc(sizeof(*div), GFP_KERNEL);
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+ if (!div) {
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+ ret = -ENOMEM;
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+ goto err_out;
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+ }
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+
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+ div->reg = base + mc->divider_reg;
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+ div->shift = mc->divider_shift;
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+ div->width = mc->divider_width;
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+ div->lock = lock;
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+
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+ div_hw = &div->hw;
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+ div_ops = &clk_divider_ops;
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+ }
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+
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+ clk = clk_register_composite(NULL, mc->name, parent_names, num_parents,
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+ mux_hw, mux_ops,
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+ div_hw, div_ops,
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+ gate_hw, gate_ops,
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+ mc->flags);
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+
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+ if (IS_ERR(clk)) {
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+ kfree(gate);
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+ kfree(mux);
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+ }
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+
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+ return clk;
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+err_out:
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+ kfree(mux);
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+
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+ return ERR_PTR(ret);
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+}
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+
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+void mtk_clk_register_composites(const struct mtk_composite *mcs,
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+ int num, void __iomem *base, spinlock_t *lock,
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+ struct clk_onecell_data *clk_data)
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+{
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+ struct clk *clk;
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+ int i;
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+
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+ for (i = 0; i < num; i++) {
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+ const struct mtk_composite *mc = &mcs[i];
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+
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+ clk = mtk_clk_register_composite(mc, base, lock);
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+
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+ if (IS_ERR(clk)) {
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+ pr_err("Failed to register clk %s: %ld\n",
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+ mc->name, PTR_ERR(clk));
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+ continue;
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+ }
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+
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+ if (clk_data)
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+ clk_data->clks[mc->id] = clk;
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+ }
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+}
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--- /dev/null
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+++ b/drivers/clk/mediatek/clk-mtk.h
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@@ -0,0 +1,159 @@
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+/*
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+ * Copyright (c) 2014 MediaTek Inc.
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+ * Author: James Liao <jamesjj.liao@mediatek.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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|
+ *
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+ * This program is distributed in the hope that it will be useful,
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|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#ifndef __DRV_CLK_MTK_H
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+#define __DRV_CLK_MTK_H
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+
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+#include <linux/regmap.h>
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+#include <linux/bitops.h>
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+#include <linux/clk.h>
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+#include <linux/clk-provider.h>
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+
|
|
+#define MAX_MUX_GATE_BIT 31
|
|
+#define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
|
|
+
|
|
+#define MHZ (1000 * 1000)
|
|
+
|
|
+struct mtk_fixed_factor {
|
|
+ int id;
|
|
+ const char *name;
|
|
+ const char *parent_name;
|
|
+ int mult;
|
|
+ int div;
|
|
+};
|
|
+
|
|
+#define FACTOR(_id, _name, _parent, _mult, _div) { \
|
|
+ .id = _id, \
|
|
+ .name = _name, \
|
|
+ .parent_name = _parent, \
|
|
+ .mult = _mult, \
|
|
+ .div = _div, \
|
|
+ }
|
|
+
|
|
+extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
|
|
+ int num, struct clk_onecell_data *clk_data);
|
|
+
|
|
+struct mtk_composite {
|
|
+ int id;
|
|
+ const char *name;
|
|
+ const char * const * parent_names;
|
|
+ const char *parent;
|
|
+ unsigned flags;
|
|
+
|
|
+ uint32_t mux_reg;
|
|
+ uint32_t divider_reg;
|
|
+ uint32_t gate_reg;
|
|
+
|
|
+ signed char mux_shift;
|
|
+ signed char mux_width;
|
|
+ signed char gate_shift;
|
|
+
|
|
+ signed char divider_shift;
|
|
+ signed char divider_width;
|
|
+
|
|
+ signed char num_parents;
|
|
+};
|
|
+
|
|
+#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \
|
|
+ .id = _id, \
|
|
+ .name = _name, \
|
|
+ .mux_reg = _reg, \
|
|
+ .mux_shift = _shift, \
|
|
+ .mux_width = _width, \
|
|
+ .gate_reg = _reg, \
|
|
+ .gate_shift = _gate, \
|
|
+ .divider_shift = -1, \
|
|
+ .parent_names = _parents, \
|
|
+ .num_parents = ARRAY_SIZE(_parents), \
|
|
+ .flags = CLK_SET_RATE_PARENT, \
|
|
+ }
|
|
+
|
|
+#define MUX(_id, _name, _parents, _reg, _shift, _width) { \
|
|
+ .id = _id, \
|
|
+ .name = _name, \
|
|
+ .mux_reg = _reg, \
|
|
+ .mux_shift = _shift, \
|
|
+ .mux_width = _width, \
|
|
+ .gate_shift = -1, \
|
|
+ .divider_shift = -1, \
|
|
+ .parent_names = _parents, \
|
|
+ .num_parents = ARRAY_SIZE(_parents), \
|
|
+ .flags = CLK_SET_RATE_PARENT, \
|
|
+ }
|
|
+
|
|
+#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \
|
|
+ .id = _id, \
|
|
+ .parent = _parent, \
|
|
+ .name = _name, \
|
|
+ .divider_reg = _div_reg, \
|
|
+ .divider_shift = _div_shift, \
|
|
+ .divider_width = _div_width, \
|
|
+ .gate_reg = _gate_reg, \
|
|
+ .gate_shift = _gate_shift, \
|
|
+ .mux_shift = -1, \
|
|
+ .flags = 0, \
|
|
+ }
|
|
+
|
|
+struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
|
|
+ void __iomem *base, spinlock_t *lock);
|
|
+
|
|
+void mtk_clk_register_composites(const struct mtk_composite *mcs,
|
|
+ int num, void __iomem *base, spinlock_t *lock,
|
|
+ struct clk_onecell_data *clk_data);
|
|
+
|
|
+struct mtk_gate_regs {
|
|
+ u32 sta_ofs;
|
|
+ u32 clr_ofs;
|
|
+ u32 set_ofs;
|
|
+};
|
|
+
|
|
+struct mtk_gate {
|
|
+ int id;
|
|
+ const char *name;
|
|
+ const char *parent_name;
|
|
+ const struct mtk_gate_regs *regs;
|
|
+ int shift;
|
|
+ const struct clk_ops *ops;
|
|
+};
|
|
+
|
|
+int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
|
|
+ int num, struct clk_onecell_data *clk_data);
|
|
+
|
|
+struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
|
|
+
|
|
+#define HAVE_RST_BAR BIT(0)
|
|
+
|
|
+struct mtk_pll_data {
|
|
+ int id;
|
|
+ const char *name;
|
|
+ uint32_t reg;
|
|
+ uint32_t pwr_reg;
|
|
+ uint32_t en_mask;
|
|
+ uint32_t pd_reg;
|
|
+ uint32_t tuner_reg;
|
|
+ int pd_shift;
|
|
+ unsigned int flags;
|
|
+ const struct clk_ops *ops;
|
|
+ u32 rst_bar_mask;
|
|
+ unsigned long fmax;
|
|
+ int pcwbits;
|
|
+ uint32_t pcw_reg;
|
|
+ int pcw_shift;
|
|
+};
|
|
+
|
|
+void __init mtk_clk_register_plls(struct device_node *node,
|
|
+ const struct mtk_pll_data *plls, int num_plls,
|
|
+ struct clk_onecell_data *clk_data);
|
|
+
|
|
+#endif /* __DRV_CLK_MTK_H */
|
|
--- /dev/null
|
|
+++ b/drivers/clk/mediatek/clk-pll.c
|
|
@@ -0,0 +1,332 @@
|
|
+/*
|
|
+ * Copyright (c) 2014 MediaTek Inc.
|
|
+ * Author: James Liao <jamesjj.liao@mediatek.com>
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License version 2 as
|
|
+ * published by the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ */
|
|
+
|
|
+#include <linux/of.h>
|
|
+#include <linux/of_address.h>
|
|
+#include <linux/io.h>
|
|
+#include <linux/slab.h>
|
|
+#include <linux/clkdev.h>
|
|
+#include <linux/delay.h>
|
|
+
|
|
+#include "clk-mtk.h"
|
|
+
|
|
+#define REG_CON0 0
|
|
+#define REG_CON1 4
|
|
+
|
|
+#define CON0_BASE_EN BIT(0)
|
|
+#define CON0_PWR_ON BIT(0)
|
|
+#define CON0_ISO_EN BIT(1)
|
|
+#define CON0_PCW_CHG BIT(31)
|
|
+
|
|
+#define AUDPLL_TUNER_EN BIT(31)
|
|
+
|
|
+#define POSTDIV_MASK 0x7
|
|
+#define INTEGER_BITS 7
|
|
+
|
|
+/*
|
|
+ * MediaTek PLLs are configured through their pcw value. The pcw value describes
|
|
+ * a divider in the PLL feedback loop which consists of 7 bits for the integer
|
|
+ * part and the remaining bits (if present) for the fractional part. Also they
|
|
+ * have a 3 bit power-of-two post divider.
|
|
+ */
|
|
+
|
|
+struct mtk_clk_pll {
|
|
+ struct clk_hw hw;
|
|
+ void __iomem *base_addr;
|
|
+ void __iomem *pd_addr;
|
|
+ void __iomem *pwr_addr;
|
|
+ void __iomem *tuner_addr;
|
|
+ void __iomem *pcw_addr;
|
|
+ const struct mtk_pll_data *data;
|
|
+};
|
|
+
|
|
+static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
|
|
+{
|
|
+ return container_of(hw, struct mtk_clk_pll, hw);
|
|
+}
|
|
+
|
|
+static int mtk_pll_is_prepared(struct clk_hw *hw)
|
|
+{
|
|
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
|
+
|
|
+ return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
|
|
+}
|
|
+
|
|
+static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
|
|
+ u32 pcw, int postdiv)
|
|
+{
|
|
+ int pcwbits = pll->data->pcwbits;
|
|
+ int pcwfbits;
|
|
+ u64 vco;
|
|
+ u8 c = 0;
|
|
+
|
|
+ /* The fractional part of the PLL divider. */
|
|
+ pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
|
|
+
|
|
+ vco = (u64)fin * pcw;
|
|
+
|
|
+ if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
|
|
+ c = 1;
|
|
+
|
|
+ vco >>= pcwfbits;
|
|
+
|
|
+ if (c)
|
|
+ vco++;
|
|
+
|
|
+ return ((unsigned long)vco + postdiv - 1) / postdiv;
|
|
+}
|
|
+
|
|
+static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
|
|
+ int postdiv)
|
|
+{
|
|
+ u32 con1, pd, val;
|
|
+ int pll_en;
|
|
+
|
|
+ /* set postdiv */
|
|
+ pd = readl(pll->pd_addr);
|
|
+ pd &= ~(POSTDIV_MASK << pll->data->pd_shift);
|
|
+ pd |= (ffs(postdiv) - 1) << pll->data->pd_shift;
|
|
+ writel(pd, pll->pd_addr);
|
|
+
|
|
+ pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
|
|
+
|
|
+ /* set pcw */
|
|
+ val = readl(pll->pcw_addr);
|
|
+
|
|
+ val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
|
|
+ pll->data->pcw_shift);
|
|
+ val |= pcw << pll->data->pcw_shift;
|
|
+ writel(val, pll->pcw_addr);
|
|
+
|
|
+ con1 = readl(pll->base_addr + REG_CON1);
|
|
+
|
|
+ if (pll_en)
|
|
+ con1 |= CON0_PCW_CHG;
|
|
+
|
|
+ writel(con1, pll->base_addr + REG_CON1);
|
|
+ if (pll->tuner_addr)
|
|
+ writel(con1 + 1, pll->tuner_addr);
|
|
+
|
|
+ if (pll_en)
|
|
+ udelay(20);
|
|
+}
|
|
+
|
|
+/*
|
|
+ * mtk_pll_calc_values - calculate good values for a given input frequency.
|
|
+ * @pll: The pll
|
|
+ * @pcw: The pcw value (output)
|
|
+ * @postdiv: The post divider (output)
|
|
+ * @freq: The desired target frequency
|
|
+ * @fin: The input frequency
|
|
+ *
|
|
+ */
|
|
+static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
|
|
+ u32 freq, u32 fin)
|
|
+{
|
|
+ unsigned long fmin = 1000 * MHZ;
|
|
+ u64 _pcw;
|
|
+ u32 val;
|
|
+
|
|
+ if (freq > pll->data->fmax)
|
|
+ freq = pll->data->fmax;
|
|
+
|
|
+ for (val = 0; val < 4; val++) {
|
|
+ *postdiv = 1 << val;
|
|
+ if (freq * *postdiv >= fmin)
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ /* _pcw = freq * postdiv / fin * 2^pcwfbits */
|
|
+ _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
|
|
+ do_div(_pcw, fin);
|
|
+
|
|
+ *pcw = (u32)_pcw;
|
|
+}
|
|
+
|
|
+static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
+ unsigned long parent_rate)
|
|
+{
|
|
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
|
+ u32 pcw = 0;
|
|
+ u32 postdiv;
|
|
+
|
|
+ mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
|
|
+ mtk_pll_set_rate_regs(pll, pcw, postdiv);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
|
|
+ unsigned long parent_rate)
|
|
+{
|
|
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
|
+ u32 postdiv;
|
|
+ u32 pcw;
|
|
+
|
|
+ postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
|
|
+ postdiv = 1 << postdiv;
|
|
+
|
|
+ pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
|
|
+ pcw &= GENMASK(pll->data->pcwbits - 1, 0);
|
|
+
|
|
+ return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
|
|
+}
|
|
+
|
|
+static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
+ unsigned long *prate)
|
|
+{
|
|
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
|
+ u32 pcw = 0;
|
|
+ int postdiv;
|
|
+
|
|
+ mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
|
|
+
|
|
+ return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
|
|
+}
|
|
+
|
|
+static int mtk_pll_prepare(struct clk_hw *hw)
|
|
+{
|
|
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
|
+ u32 r;
|
|
+
|
|
+ r = readl(pll->pwr_addr) | CON0_PWR_ON;
|
|
+ writel(r, pll->pwr_addr);
|
|
+ udelay(1);
|
|
+
|
|
+ r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
|
|
+ writel(r, pll->pwr_addr);
|
|
+ udelay(1);
|
|
+
|
|
+ r = readl(pll->base_addr + REG_CON0);
|
|
+ r |= pll->data->en_mask;
|
|
+ writel(r, pll->base_addr + REG_CON0);
|
|
+
|
|
+ if (pll->tuner_addr) {
|
|
+ r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
|
|
+ writel(r, pll->tuner_addr);
|
|
+ }
|
|
+
|
|
+ udelay(20);
|
|
+
|
|
+ if (pll->data->flags & HAVE_RST_BAR) {
|
|
+ r = readl(pll->base_addr + REG_CON0);
|
|
+ r |= pll->data->rst_bar_mask;
|
|
+ writel(r, pll->base_addr + REG_CON0);
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void mtk_pll_unprepare(struct clk_hw *hw)
|
|
+{
|
|
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
|
+ u32 r;
|
|
+
|
|
+ if (pll->data->flags & HAVE_RST_BAR) {
|
|
+ r = readl(pll->base_addr + REG_CON0);
|
|
+ r &= ~pll->data->rst_bar_mask;
|
|
+ writel(r, pll->base_addr + REG_CON0);
|
|
+ }
|
|
+
|
|
+ if (pll->tuner_addr) {
|
|
+ r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
|
|
+ writel(r, pll->tuner_addr);
|
|
+ }
|
|
+
|
|
+ r = readl(pll->base_addr + REG_CON0);
|
|
+ r &= ~CON0_BASE_EN;
|
|
+ writel(r, pll->base_addr + REG_CON0);
|
|
+
|
|
+ r = readl(pll->pwr_addr) | CON0_ISO_EN;
|
|
+ writel(r, pll->pwr_addr);
|
|
+
|
|
+ r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
|
|
+ writel(r, pll->pwr_addr);
|
|
+}
|
|
+
|
|
+static const struct clk_ops mtk_pll_ops = {
|
|
+ .is_prepared = mtk_pll_is_prepared,
|
|
+ .prepare = mtk_pll_prepare,
|
|
+ .unprepare = mtk_pll_unprepare,
|
|
+ .recalc_rate = mtk_pll_recalc_rate,
|
|
+ .round_rate = mtk_pll_round_rate,
|
|
+ .set_rate = mtk_pll_set_rate,
|
|
+};
|
|
+
|
|
+static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
|
|
+ void __iomem *base)
|
|
+{
|
|
+ struct mtk_clk_pll *pll;
|
|
+ struct clk_init_data init;
|
|
+ struct clk *clk;
|
|
+ const char *parent_name = "clk26m";
|
|
+
|
|
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
|
+ if (!pll)
|
|
+ return ERR_PTR(-ENOMEM);
|
|
+
|
|
+ pll->base_addr = base + data->reg;
|
|
+ pll->pwr_addr = base + data->pwr_reg;
|
|
+ pll->pd_addr = base + data->pd_reg;
|
|
+ pll->pcw_addr = base + data->pcw_reg;
|
|
+ if (data->tuner_reg)
|
|
+ pll->tuner_addr = base + data->tuner_reg;
|
|
+ pll->hw.init = &init;
|
|
+ pll->data = data;
|
|
+
|
|
+ init.name = data->name;
|
|
+ init.ops = &mtk_pll_ops;
|
|
+ init.parent_names = &parent_name;
|
|
+ init.num_parents = 1;
|
|
+
|
|
+ clk = clk_register(NULL, &pll->hw);
|
|
+
|
|
+ if (IS_ERR(clk))
|
|
+ kfree(pll);
|
|
+
|
|
+ return clk;
|
|
+}
|
|
+
|
|
+void __init mtk_clk_register_plls(struct device_node *node,
|
|
+ const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data)
|
|
+{
|
|
+ void __iomem *base;
|
|
+ int r, i;
|
|
+ struct clk *clk;
|
|
+
|
|
+ base = of_iomap(node, 0);
|
|
+ if (!base) {
|
|
+ pr_err("%s(): ioremap failed\n", __func__);
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ for (i = 0; i < num_plls; i++) {
|
|
+ const struct mtk_pll_data *pll = &plls[i];
|
|
+
|
|
+ clk = mtk_clk_register_pll(pll, base);
|
|
+
|
|
+ if (IS_ERR(clk)) {
|
|
+ pr_err("Failed to register clk %s: %ld\n",
|
|
+ pll->name, PTR_ERR(clk));
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ clk_data->clks[pll->id] = clk;
|
|
+ }
|
|
+
|
|
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
|
+ if (r)
|
|
+ pr_err("%s(): could not register clock provider: %d\n",
|
|
+ __func__, r);
|
|
+}
|