mirror of https://github.com/hak5/openwrt-owl.git
214 lines
5.5 KiB
Diff
214 lines
5.5 KiB
Diff
From a4fbc2dec67a5d760e25e3c3a6c392191a5405c6 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Tue, 22 Nov 2011 14:11:19 +0100
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Subject: [PATCH 13/35] MIPS: ath79: add PCI IRQ handling code for AR724X SoCs
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The PCI Host Controller of the AR724x SoC has a
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built-in IRQ controller. The current code does
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not supports that, so the IRQ lines wired to this
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controller are not usable. This leads to failed
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'request_irq' calls:
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ath9k 0000:00:00.0: request_irq failed
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ath9k: probe of 0000:00:00.0 failed with error -89
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This patch adds support for the IRQ controller
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in order to make PCI IRQs work.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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v2: - move the interrupt controller related defines from
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the workaround patch
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---
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arch/mips/ath79/pci.c | 3 +-
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arch/mips/include/asm/mach-ath79/pci.h | 4 +-
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arch/mips/pci/pci-ar724x.c | 118 +++++++++++++++++++++++++++++++-
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3 files changed, 120 insertions(+), 5 deletions(-)
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--- a/arch/mips/ath79/pci.c
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+++ b/arch/mips/ath79/pci.c
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@@ -10,6 +10,7 @@
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#include <linux/pci.h>
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#include <asm/mach-ath79/ath79.h>
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+#include <asm/mach-ath79/irq.h>
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#include <asm/mach-ath79/pci.h>
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#include "pci.h"
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@@ -50,7 +51,7 @@ int pcibios_plat_dev_init(struct pci_dev
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int __init ath79_register_pci(void)
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{
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if (soc_is_ar724x())
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- return ar724x_pcibios_init();
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+ return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
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return -ENODEV;
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}
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--- a/arch/mips/include/asm/mach-ath79/pci.h
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+++ b/arch/mips/include/asm/mach-ath79/pci.h
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@@ -12,9 +12,9 @@
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#define __ASM_MACH_ATH79_PCI_H
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#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
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-int ar724x_pcibios_init(void);
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+int ar724x_pcibios_init(int irq);
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#else
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-static inline int ar724x_pcibios_init(void) { return 0 };
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+static inline int ar724x_pcibios_init(int irq) { return 0 };
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#endif
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#endif /* __ASM_MACH_ATH79_PCI_H */
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--- a/arch/mips/pci/pci-ar724x.c
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+++ b/arch/mips/pci/pci-ar724x.c
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@@ -8,19 +8,32 @@
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* by the Free Software Foundation.
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*/
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+#include <linux/irq.h>
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#include <linux/pci.h>
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#include <asm/mach-ath79/ath79.h>
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+#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/pci.h>
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#define AR724X_PCI_CFG_BASE 0x14000000
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#define AR724X_PCI_CFG_SIZE 0x1000
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+#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
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+#define AR724X_PCI_CTRL_SIZE 0x100
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+
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#define AR724X_PCI_MEM_BASE 0x10000000
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#define AR724X_PCI_MEM_SIZE 0x08000000
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+#define AR724X_PCI_REG_INT_STATUS 0x4c
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+#define AR724X_PCI_REG_INT_MASK 0x50
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+
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+#define AR724X_PCI_INT_DEV0 BIT(14)
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+
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+#define AR724X_PCI_IRQ_COUNT 1
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+
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#define AR7240_BAR0_WAR_VALUE 0xffff
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static DEFINE_SPINLOCK(ar724x_pci_lock);
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static void __iomem *ar724x_pci_devcfg_base;
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+static void __iomem *ar724x_pci_ctrl_base;
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static u32 ar724x_pci_bar0_value;
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static bool ar724x_pci_bar0_is_cached;
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@@ -164,14 +177,115 @@ static struct pci_controller ar724x_pci_
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.mem_resource = &ar724x_mem_resource,
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};
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-int __init ar724x_pcibios_init(void)
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+static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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+{
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+ void __iomem *base;
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+ u32 pending;
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+
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+ base = ar724x_pci_ctrl_base;
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+
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+ pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
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+ __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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+
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+ if (pending & AR724X_PCI_INT_DEV0)
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+ generic_handle_irq(ATH79_PCI_IRQ(0));
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+
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+ else
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+ spurious_interrupt();
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+}
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+
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+static void ar724x_pci_irq_unmask(struct irq_data *d)
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+{
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+ void __iomem *base;
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+ u32 t;
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+
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+ base = ar724x_pci_ctrl_base;
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+
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+ switch (d->irq) {
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+ case ATH79_PCI_IRQ(0):
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+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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+ __raw_writel(t | AR724X_PCI_INT_DEV0,
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+ base + AR724X_PCI_REG_INT_MASK);
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+ /* flush write */
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+ __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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+ }
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+}
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+
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+static void ar724x_pci_irq_mask(struct irq_data *d)
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+{
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+ void __iomem *base;
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+ u32 t;
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+
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+ base = ar724x_pci_ctrl_base;
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+
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+ switch (d->irq) {
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+ case ATH79_PCI_IRQ(0):
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+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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+ __raw_writel(t & ~AR724X_PCI_INT_DEV0,
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+ base + AR724X_PCI_REG_INT_MASK);
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+
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+ /* flush write */
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+ __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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+
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+ t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
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+ __raw_writel(t | AR724X_PCI_INT_DEV0,
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+ base + AR724X_PCI_REG_INT_STATUS);
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+
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+ /* flush write */
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+ __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
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+ }
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+}
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+
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+static struct irq_chip ar724x_pci_irq_chip = {
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+ .name = "AR724X PCI ",
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+ .irq_mask = ar724x_pci_irq_mask,
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+ .irq_unmask = ar724x_pci_irq_unmask,
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+ .irq_mask_ack = ar724x_pci_irq_mask,
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+};
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+
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+static void __init ar724x_pci_irq_init(int irq)
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+{
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+ void __iomem *base;
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+ int i;
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+
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+ base = ar724x_pci_ctrl_base;
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+
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+ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
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+ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
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+
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+ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
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+
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+ for (i = ATH79_PCI_IRQ_BASE;
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+ i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++)
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+ irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
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+ handle_level_irq);
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+
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+ irq_set_chained_handler(irq, ar724x_pci_irq_handler);
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+}
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+
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+int __init ar724x_pcibios_init(int irq)
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{
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+ int ret;
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+
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+ ret = -ENOMEM;
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+
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ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
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AR724X_PCI_CFG_SIZE);
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if (ar724x_pci_devcfg_base == NULL)
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- return -ENOMEM;
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+ goto err;
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+ ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE,
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+ AR724X_PCI_CTRL_SIZE);
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+ if (ar724x_pci_ctrl_base == NULL)
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+ goto err_unmap_devcfg;
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+
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+ ar724x_pci_irq_init(irq);
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register_pci_controller(&ar724x_pci_controller);
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return PCIBIOS_SUCCESSFUL;
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+
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+err_unmap_devcfg:
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+ iounmap(ar724x_pci_devcfg_base);
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+err:
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+ return ret;
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}
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