mirror of https://github.com/hak5/openwrt-owl.git
370 lines
12 KiB
C
370 lines
12 KiB
C
/*
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* Broadcom device-specific manifest constants.
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*
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* Copyright 2006, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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* $Id: bcmdevs.h,v 1.1.1.17 2006/04/15 01:29:08 michael Exp $
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*/
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#ifndef _BCMDEVS_H
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#define _BCMDEVS_H
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#include "bcm4710.h"
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/* Known PCI vendor Id's */
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#define VENDOR_EPIGRAM 0xfeda
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#define VENDOR_BROADCOM 0x14e4
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#define VENDOR_3COM 0x10b7
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#define VENDOR_NETGEAR 0x1385
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#define VENDOR_DIAMOND 0x1092
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#define VENDOR_DELL 0x1028
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#define VENDOR_HP 0x0e11
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#define VENDOR_APPLE 0x106b
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/* PCI Device Id's */
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#define BCM4210_DEVICE_ID 0x1072 /* never used */
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#define BCM4211_DEVICE_ID 0x4211
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#define BCM4230_DEVICE_ID 0x1086 /* never used */
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#define BCM4231_DEVICE_ID 0x4231
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#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
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#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
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#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
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#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
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#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
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#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
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#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
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#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
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#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
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#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
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#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
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#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
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#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
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#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
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#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
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#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
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#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
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#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
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#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
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#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
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#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
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#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
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#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
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#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
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#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */
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#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
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#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
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#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
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#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
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#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
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#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
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#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
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#define BCM4306_D11G_ID2 0x4325
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#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
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#define BCM4306_UART_ID 0x4322 /* 4306 uart */
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#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
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#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
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#define BCM4309_PKG_ID 1 /* 4309 package id */
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#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
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#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
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#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
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#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
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#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
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#define BCM4303_PKG_ID 2 /* 4303 package id */
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#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
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#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
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#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
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#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
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#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */
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#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
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#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
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#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
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#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */
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#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
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#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Hgz band id */
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#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
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#define BCM4331_CHIP_ID 0x4331 /* 4331 chip common chipid */
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#define BCM4331_D11N2G_ID 0x4330 /* 4331 802.11n 2.4Ghz band id */
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#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
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#define BCM4331_D11N5G_ID 0x4332 /* 4331 802.11n 5Ghz band id */
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#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
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#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
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#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
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#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
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#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
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#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
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#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
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#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
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#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
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#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
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#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
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#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
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#define BCM4328_CHIP_ID 0x4328 /* bcm4328 chipcommon chipid */
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#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
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#define BCM43XX_JTAGM_ID 0x43f1 /* 43xx jtagm device id */
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#define BCM43XXOLD_JTAGM_ID 0x4331 /* 43xx old jtagm device id */
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#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
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#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
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#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
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#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
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/* PCMCIA vendor Id's */
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#define VENDOR_BROADCOM_PCMCIA 0x02d0
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/* SDIO vendor Id's */
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#define VENDOR_BROADCOM_SDIO 0x00BF
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/* boardflags */
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#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
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#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
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#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
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#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
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#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
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#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
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#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
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#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
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#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
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#define BFL_FEM 0x0800 /* This board supports the Front End Module */
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#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
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#define BFL_HGPA 0x2000 /* This board has a high gain PA */
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#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
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#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
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/* boardflags2 */
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#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */
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#define BFL2_SSWITCH_AVAIL 0x00000002 /* This board has a superswitch for > 2 antennas */
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#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits TX Power Control to be enabled */
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/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
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#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
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#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
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#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
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#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
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#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
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#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
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#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
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#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
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#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
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/* power control defines */
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#define PLL_DELAY 150 /* us pll on delay */
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#define FREF_DELAY 200 /* us fref change delay */
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#define MIN_SLOW_CLK 32 /* us Slow clock period */
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#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
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/* Reference Board Types */
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#define BU4710_BOARD 0x0400
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#define VSIM4710_BOARD 0x0401
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#define QT4710_BOARD 0x0402
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#define BU4309_BOARD 0x040a
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#define BCM94309CB_BOARD 0x040b
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#define BCM94309MP_BOARD 0x040c
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#define BCM4309AP_BOARD 0x040d
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#define BCM94302MP_BOARD 0x040e
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#define BU4306_BOARD 0x0416
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#define BCM94306CB_BOARD 0x0417
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#define BCM94306MP_BOARD 0x0418
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#define BCM94710D_BOARD 0x041a
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#define BCM94710R1_BOARD 0x041b
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#define BCM94710R4_BOARD 0x041c
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#define BCM94710AP_BOARD 0x041d
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#define BU2050_BOARD 0x041f
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#define BCM94309G_BOARD 0x0421
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#define BU4704_BOARD 0x0423
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#define BU4702_BOARD 0x0424
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#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
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#define BCM94702MN_BOARD 0x0428
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/* BCM4702 1U CompactPCI Board */
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#define BCM94702CPCI_BOARD 0x0429
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/* BCM4702 with BCM95380 VLAN Router */
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#define BCM95380RR_BOARD 0x042a
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/* cb4306 with SiGe PA */
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#define BCM94306CBSG_BOARD 0x042b
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/* cb4306 with SiGe PA */
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#define PCSG94306_BOARD 0x042d
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/* bu4704 with sdram */
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#define BU4704SD_BOARD 0x042e
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/* Dual 11a/11g Router */
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#define BCM94704AGR_BOARD 0x042f
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/* 11a-only minipci */
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#define BCM94308MP_BOARD 0x0430
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#define BU4712_BOARD 0x0444
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#define BU4712SD_BOARD 0x045d
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#define BU4712L_BOARD 0x045f
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/* BCM4712 boards */
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#define BCM94712AP_BOARD 0x0445
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#define BCM94712P_BOARD 0x0446
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/* BCM4318 boards */
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#define BU4318_BOARD 0x0447
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#define CB4318_BOARD 0x0448
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#define MPG4318_BOARD 0x0449
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#define MP4318_BOARD 0x044a
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#define SD4318_BOARD 0x044b
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/* BCM63XX boards */
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#define BCM96338_BOARD 0x6338
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#define BCM96348_BOARD 0x6348
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/* Another mp4306 with SiGe */
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#define BCM94306P_BOARD 0x044c
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/* mp4303 */
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#define BCM94303MP_BOARD 0x044e
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/* mpsgh4306 */
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#define BCM94306MPSGH_BOARD 0x044f
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/* BRCM 4306 w/ Front End Modules */
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#define BCM94306MPM 0x0450
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#define BCM94306MPL 0x0453
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/* 4712agr */
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#define BCM94712AGR_BOARD 0x0451
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/* pcmcia 4303 */
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#define PC4303_BOARD 0x0454
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/* 5350K */
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#define BCM95350K_BOARD 0x0455
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/* 5350R */
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#define BCM95350R_BOARD 0x0456
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/* 4306mplna */
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#define BCM94306MPLNA_BOARD 0x0457
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/* 4320 boards */
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#define BU4320_BOARD 0x0458
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#define BU4320S_BOARD 0x0459
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#define BCM94320PH_BOARD 0x045a
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/* 4306mph */
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#define BCM94306MPH_BOARD 0x045b
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/* 4306pciv */
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#define BCM94306PCIV_BOARD 0x045c
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#define BU4712SD_BOARD 0x045d
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#define BCM94320PFLSH_BOARD 0x045e
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#define BU4712L_BOARD 0x045f
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#define BCM94712LGR_BOARD 0x0460
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#define BCM94320R_BOARD 0x0461
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#define BU5352_BOARD 0x0462
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#define BCM94318MPGH_BOARD 0x0463
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#define BU4311_BOARD 0x0464
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#define BCM94311MC_BOARD 0x0465
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#define BCM94311MCAG_BOARD 0x0466
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#define BCM95352GR_BOARD 0x0467
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/* bcm95351agr */
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#define BCM95351AGR_BOARD 0x0470
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/* bcm94704mpcb */
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#define BCM94704MPCB_BOARD 0x0472
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/* 4785 boards */
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#define BU4785_BOARD 0x0478
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/* 4321 boards */
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#define BU4321_BOARD 0x046b
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#define BU4321E_BOARD 0x047c
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#define MP4321_BOARD 0x046c
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#define CB2_4321_BOARD 0x046d
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#define MC4321_BOARD 0x046e
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/* # of GPIO pins */
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#define GPIO_NUMPINS 16
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/* radio ID codes */
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#define NORADIO_ID 0xe4f5
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#define NORADIO_IDCODE 0x4e4f5246
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#define BCM2050_ID 0x2050
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#define BCM2050_IDCODE 0x02050000
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#define BCM2050A0_IDCODE 0x1205017f
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#define BCM2050A1_IDCODE 0x2205017f
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#define BCM2050R8_IDCODE 0x8205017f
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#define BCM2055_ID 0x2055
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#define BCM2055_IDCODE 0x02055000
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#define BCM2055A0_IDCODE 0x1205517f
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#define BCM2060_ID 0x2060
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#define BCM2060_IDCODE 0x02060000
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#define BCM2060WW_IDCODE 0x1206017f
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#define BCM2062_ID 0x2062
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#define BCM2062_IDCODE 0x02062000
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#define BCM2062A0_IDCODE 0x0206217f
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/* parts of an idcode: */
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#define IDCODE_MFG_MASK 0x00000fff
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#define IDCODE_MFG_SHIFT 0
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#define IDCODE_ID_MASK 0x0ffff000
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#define IDCODE_ID_SHIFT 12
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#define IDCODE_REV_MASK 0xf0000000
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#define IDCODE_REV_SHIFT 28
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#endif /* _BCMDEVS_H */
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