mirror of https://github.com/hak5/openwrt-owl.git
259 lines
6.0 KiB
C
259 lines
6.0 KiB
C
/*
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* Gemini EHCI Host Controller driver
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*
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* Copyright (C) 2014 Roman Yeryomin <roman@advem.lv>
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* Copyright (C) 2012 Tobias Waldvogel
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* based on GPLd code from Sony Computer Entertainment Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/kernel.h>
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#include <linux/hrtimer.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/usb.h>
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#include <linux/usb/hcd.h>
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#include <linux/usb/ehci_pdriver.h>
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#include <mach/hardware.h>
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#include <mach/global_reg.h>
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#include "ehci.h"
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#define DRV_NAME "ehci-fotg2"
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#define HCD_MISC 0x40
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#define OTGC_SCR 0x80
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#define OTGC_INT_STS 0x84
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#define OTGC_INT_EN 0x88
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#define GLOBAL_ISR 0xC0
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#define GLOBAL_ICR 0xC4
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#define GLOBAL_INT_POLARITY (1 << 3)
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#define GLOBAL_INT_MASK_HC (1 << 2)
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#define GLOBAL_INT_MASK_OTG (1 << 1)
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#define GLOBAL_INT_MASK_DEV (1 << 0)
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#define OTGC_SCR_ID (1 << 21)
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#define OTGC_SCR_CROLE (1 << 20)
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#define OTGC_SCR_VBUS_VLD (1 << 19)
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#define OTGC_SCR_A_SRP_RESP_TYPE (1 << 8)
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#define OTGC_SCR_A_SRP_DET_EN (1 << 7)
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#define OTGC_SCR_A_SET_B_HNP_EN (1 << 6)
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#define OTGC_SCR_A_BUS_DROP (1 << 5)
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#define OTGC_SCR_A_BUS_REQ (1 << 4)
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#define OTGC_INT_APLGRMV (1 << 12)
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#define OTGC_INT_BPLGRMV (1 << 11)
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#define OTGC_INT_OVC (1 << 10)
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#define OTGC_INT_IDCHG (1 << 9)
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#define OTGC_INT_RLCHG (1 << 8)
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#define OTGC_INT_AVBUSERR (1 << 5)
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#define OTGC_INT_ASRPDET (1 << 4)
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#define OTGC_INT_BSRPDN (1 << 0)
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#define OTGC_INT_A_TYPE ( \
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OTGC_INT_ASRPDET | \
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OTGC_INT_AVBUSERR | \
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OTGC_INT_OVC | \
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OTGC_INT_RLCHG | \
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OTGC_INT_IDCHG | \
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OTGC_INT_APLGRMV \
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)
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#define OTGC_INT_B_TYPE ( \
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OTGC_INT_AVBUSERR | \
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OTGC_INT_OVC | \
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OTGC_INT_RLCHG | \
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OTGC_INT_IDCHG \
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)
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static void fotg2_otg_init(struct usb_hcd *hcd)
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{
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u32 val;
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writel(GLOBAL_INT_POLARITY | GLOBAL_INT_MASK_HC |
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GLOBAL_INT_MASK_OTG | GLOBAL_INT_MASK_DEV,
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hcd->regs + GLOBAL_ICR);
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val = readl(hcd->regs + OTGC_SCR);
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val &= ~(OTGC_SCR_A_SRP_RESP_TYPE | OTGC_SCR_A_SRP_DET_EN |
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OTGC_SCR_A_BUS_DROP | OTGC_SCR_A_SET_B_HNP_EN);
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val |= OTGC_SCR_A_BUS_REQ;
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writel(val, hcd->regs + OTGC_SCR);
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writel(OTGC_INT_A_TYPE, hcd->regs + OTGC_INT_EN);
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/* setup MISC register, fixes timing problems */
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val = readl(hcd->regs + HCD_MISC);
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val |= 0xD;
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writel(val, hcd->regs + HCD_MISC);
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writel(~0, hcd->regs + GLOBAL_ISR);
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writel(~0, hcd->regs + OTGC_INT_STS);
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}
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static int fotg2_ehci_reset(struct usb_hcd *hcd)
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{
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int retval;
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retval = ehci_setup(hcd);
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if (retval)
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return retval;
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writel(GLOBAL_INT_POLARITY, hcd->regs + GLOBAL_ICR);
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return 0;
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}
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static const struct hc_driver fotg2_ehci_hc_driver = {
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.description = hcd_name,
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.product_desc = "FOTG2 EHCI Host Controller",
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.hcd_priv_size = sizeof(struct ehci_hcd),
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.irq = ehci_irq,
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.flags = HCD_MEMORY | HCD_USB2,
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.reset = fotg2_ehci_reset,
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.start = ehci_run,
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.stop = ehci_stop,
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.shutdown = ehci_shutdown,
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.urb_enqueue = ehci_urb_enqueue,
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.urb_dequeue = ehci_urb_dequeue,
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.endpoint_disable = ehci_endpoint_disable,
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.endpoint_reset = ehci_endpoint_reset,
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.get_frame_number = ehci_get_frame,
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.hub_status_data = ehci_hub_status_data,
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.hub_control = ehci_hub_control,
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#if defined(CONFIG_PM)
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.bus_suspend = ehci_bus_suspend,
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.bus_resume = ehci_bus_resume,
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#endif
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.relinquish_port = ehci_relinquish_port,
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.port_handed_over = ehci_port_handed_over,
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.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
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};
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static irqreturn_t fotg2_ehci_irq(int irq, void *data)
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{
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struct usb_hcd *hcd = data;
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u32 icr, sts;
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irqreturn_t retval;
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icr = readl(hcd->regs + GLOBAL_ICR);
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writel(GLOBAL_INT_POLARITY | GLOBAL_INT_MASK_HC |
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GLOBAL_INT_MASK_OTG | GLOBAL_INT_MASK_DEV,
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hcd->regs + GLOBAL_ICR);
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retval = IRQ_NONE;
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sts = ~icr;
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sts &= GLOBAL_INT_MASK_HC | GLOBAL_INT_MASK_OTG | GLOBAL_INT_MASK_DEV;
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sts &= readl(hcd->regs + GLOBAL_ISR);
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writel(sts, hcd->regs + GLOBAL_ISR);
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if (unlikely(sts & GLOBAL_INT_MASK_DEV)) {
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ehci_warn(hcd_to_ehci(hcd),
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"Received unexpected irq for device role\n");
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retval = IRQ_HANDLED;
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}
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if (unlikely(sts & GLOBAL_INT_MASK_OTG)) {
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u32 otg_sts;
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otg_sts = readl(hcd->regs + OTGC_INT_STS);
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writel(otg_sts, hcd->regs + OTGC_INT_STS);
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ehci_warn(hcd_to_ehci(hcd),
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"Received unexpected irq for OTG management\n");
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retval = IRQ_HANDLED;
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}
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if (sts & GLOBAL_INT_MASK_HC) {
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retval = IRQ_NONE;
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}
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writel(icr, hcd->regs + GLOBAL_ICR);
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return retval;
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}
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static int fotg2_ehci_probe(struct platform_device *pdev)
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{
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struct usb_hcd *hcd;
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struct resource *res;
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int irq , err;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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pr_err("no irq provided");
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return irq;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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pr_err("no memory resource provided");
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return -ENXIO;
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}
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hcd = usb_create_hcd(&fotg2_ehci_hc_driver, &pdev->dev,
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dev_name(&pdev->dev));
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if (!hcd)
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return -ENOMEM;
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hcd->rsrc_start = res->start;
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hcd->rsrc_len = resource_size(res);
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hcd->regs = devm_request_and_ioremap(&pdev->dev, res);
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if (!hcd->regs) {
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err = -ENOMEM;
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goto err_put_hcd;
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}
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hcd->has_tt = 1;
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hcd_to_ehci(hcd)->caps = hcd->regs;
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fotg2_otg_init(hcd);
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err = request_irq(irq, &fotg2_ehci_irq, IRQF_SHARED, "fotg2", hcd);
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if (err)
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goto err_put_hcd;
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err = usb_add_hcd(hcd, irq, IRQF_SHARED);
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if (err)
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goto err_put_hcd;
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platform_set_drvdata(pdev, hcd);
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return 0;
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err_put_hcd:
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usb_put_hcd(hcd);
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return err;
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}
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static int fotg2_ehci_remove(struct platform_device *pdev)
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{
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struct usb_hcd *hcd = platform_get_drvdata(pdev);
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writel(GLOBAL_INT_POLARITY | GLOBAL_INT_MASK_HC |
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GLOBAL_INT_MASK_OTG | GLOBAL_INT_MASK_DEV,
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hcd->regs + GLOBAL_ICR);
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free_irq(hcd->irq, hcd);
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usb_remove_hcd(hcd);
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usb_put_hcd(hcd);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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MODULE_ALIAS("platform:" DRV_NAME);
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static struct platform_driver ehci_fotg2_driver = {
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.probe = fotg2_ehci_probe,
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.remove = fotg2_ehci_remove,
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.driver.name = DRV_NAME,
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};
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