mirror of https://github.com/hak5/openwrt-owl.git
1371 lines
40 KiB
Diff
1371 lines
40 KiB
Diff
From db5029d82c4f0685438ea38eb3fbaadac46a22ba Mon Sep 17 00:00:00 2001
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From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Date: Wed, 12 Jun 2013 18:02:19 -0300
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Subject: [PATCH 059/203] ARM: mvebu: Relocate Armada 370/XP PCIe device tree
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nodes
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Now that mbus has been added to the device tree, it's possible to
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move the PCIe nodes out of internal registers, placing it directly
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below the mbus. This is a more accurate representation of the
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hardware.
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Moving the PCIe nodes, we now need to introduce an extra cell to
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encode the window target ID and attribute. Since this depends on
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the PCIe port, we split the ranges translation entries, to correspond
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to each MBus window.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Tested-by: Andrew Lunn <andrew@lunn.ch>
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Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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---
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arch/arm/boot/dts/armada-370-mirabox.dts | 32 +-
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arch/arm/boot/dts/armada-370-xp.dtsi | 2 +
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arch/arm/boot/dts/armada-370.dtsi | 101 +++---
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arch/arm/boot/dts/armada-xp-db.dts | 67 ++--
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arch/arm/boot/dts/armada-xp-gp.dts | 42 +--
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arch/arm/boot/dts/armada-xp-mv78230.dtsi | 222 ++++++------
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arch/arm/boot/dts/armada-xp-mv78260.dtsi | 261 ++++++++-------
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arch/arm/boot/dts/armada-xp-mv78460.dtsi | 409 ++++++++++++-----------
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arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 18 +-
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9 files changed, 612 insertions(+), 542 deletions(-)
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--- a/arch/arm/boot/dts/armada-370-mirabox.dts
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+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
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@@ -28,6 +28,22 @@
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
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+ pcie-controller {
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+ status = "okay";
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+
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+ /* Internal mini-PCIe connector */
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+ pcie@1,0 {
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+ /* Port 0, Lane 0 */
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+ status = "okay";
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+ };
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+
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+ /* Connected on the PCB to a USB 3.0 XHCI controller */
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+ pcie@2,0 {
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+ /* Port 1, Lane 0 */
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+ status = "okay";
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+ };
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+ };
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+
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internal-regs {
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serial@12000 {
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clock-frequency = <200000000>;
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@@ -123,22 +139,6 @@
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reg = <0x25>;
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};
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};
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-
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- pcie-controller {
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- status = "okay";
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-
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- /* Internal mini-PCIe connector */
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- pcie@1,0 {
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- /* Port 0, Lane 0 */
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- status = "okay";
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- };
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-
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- /* Connected on the PCB to a USB 3.0 XHCI controller */
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- pcie@2,0 {
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- /* Port 1, Lane 0 */
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- status = "okay";
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- };
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- };
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};
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};
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};
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--- a/arch/arm/boot/dts/armada-370-xp.dtsi
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+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
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@@ -35,6 +35,8 @@
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#size-cells = <1>;
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controller = <&mbusc>;
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interrupt-parent = <&mpic>;
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+ pcie-mem-aperture = <0xe0000000 0x8000000>;
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+ pcie-io-aperture = <0xe8000000 0x100000>;
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devbus-bootcs {
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compatible = "marvell,mvebu-devbus";
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--- a/arch/arm/boot/dts/armada-370.dtsi
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+++ b/arch/arm/boot/dts/armada-370.dtsi
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@@ -36,6 +36,59 @@
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reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
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};
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+ pcie-controller {
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+ compatible = "marvell,armada-370-pcie";
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+ status = "disabled";
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+ device_type = "pci";
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+
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ bus-range = <0x00 0xff>;
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+
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+ ranges =
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+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
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+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
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+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
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+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
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+ 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
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+ 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
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+
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+ pcie@1,0 {
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+ device_type = "pci";
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+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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+ reg = <0x0800 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &mpic 58>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <0>;
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+ clocks = <&gateclk 5>;
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+ status = "disabled";
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+ };
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+
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+ pcie@2,0 {
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+ device_type = "pci";
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+ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
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+ reg = <0x1000 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &mpic 62>;
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+ marvell,pcie-port = <1>;
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+ marvell,pcie-lane = <0>;
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+ clocks = <&gateclk 9>;
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+ status = "disabled";
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+ };
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+ };
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+
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internal-regs {
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system-controller@18200 {
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compatible = "marvell,armada-370-xp-system-controller";
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@@ -174,54 +227,6 @@
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0x18304 0x4>;
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status = "okay";
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};
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-
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- pcie-controller {
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- compatible = "marvell,armada-370-pcie";
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- status = "disabled";
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- device_type = "pci";
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-
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- #address-cells = <3>;
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- #size-cells = <2>;
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-
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- bus-range = <0x00 0xff>;
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-
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- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
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- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
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- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
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- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
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-
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- pcie@1,0 {
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- device_type = "pci";
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- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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- reg = <0x0800 0 0 0 0>;
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- #address-cells = <3>;
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- #size-cells = <2>;
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- #interrupt-cells = <1>;
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- ranges;
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- interrupt-map-mask = <0 0 0 0>;
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- interrupt-map = <0 0 0 0 &mpic 58>;
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- marvell,pcie-port = <0>;
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- marvell,pcie-lane = <0>;
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- clocks = <&gateclk 5>;
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- status = "disabled";
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- };
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-
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- pcie@2,0 {
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- device_type = "pci";
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- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
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- reg = <0x1000 0 0 0 0>;
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- #address-cells = <3>;
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- #size-cells = <2>;
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- #interrupt-cells = <1>;
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- ranges;
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- interrupt-map-mask = <0 0 0 0>;
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- interrupt-map = <0 0 0 0 &mpic 62>;
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- marvell,pcie-port = <1>;
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- marvell,pcie-lane = <0>;
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- clocks = <&gateclk 9>;
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- status = "disabled";
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- };
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- };
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};
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};
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};
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--- a/arch/arm/boot/dts/armada-xp-db.dts
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+++ b/arch/arm/boot/dts/armada-xp-db.dts
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@@ -62,6 +62,39 @@
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};
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};
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+ pcie-controller {
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+ status = "okay";
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+
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+ /*
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+ * All 6 slots are physically present as
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+ * standard PCIe slots on the board.
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+ */
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+ pcie@1,0 {
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+ /* Port 0, Lane 0 */
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+ status = "okay";
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+ };
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+ pcie@2,0 {
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+ /* Port 0, Lane 1 */
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+ status = "okay";
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+ };
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+ pcie@3,0 {
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+ /* Port 0, Lane 2 */
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+ status = "okay";
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+ };
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+ pcie@4,0 {
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+ /* Port 0, Lane 3 */
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+ status = "okay";
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+ };
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+ pcie@9,0 {
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+ /* Port 2, Lane 0 */
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+ status = "okay";
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+ };
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+ pcie@10,0 {
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+ /* Port 3, Lane 0 */
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+ status = "okay";
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+ };
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+ };
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+
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internal-regs {
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serial@12000 {
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clock-frequency = <250000000>;
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@@ -155,40 +188,6 @@
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spi-max-frequency = <20000000>;
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};
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};
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-
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- pcie-controller {
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- status = "okay";
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-
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- /*
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- * All 6 slots are physically present as
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- * standard PCIe slots on the board.
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- */
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- pcie@1,0 {
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- /* Port 0, Lane 0 */
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- status = "okay";
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- };
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- pcie@2,0 {
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- /* Port 0, Lane 1 */
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- status = "okay";
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- };
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- pcie@3,0 {
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- /* Port 0, Lane 2 */
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- status = "okay";
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- };
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- pcie@4,0 {
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- /* Port 0, Lane 3 */
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- status = "okay";
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- };
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- pcie@9,0 {
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- /* Port 2, Lane 0 */
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- status = "okay";
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- };
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- pcie@10,0 {
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- /* Port 3, Lane 0 */
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- status = "okay";
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- };
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- };
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-
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};
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};
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};
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--- a/arch/arm/boot/dts/armada-xp-gp.dts
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+++ b/arch/arm/boot/dts/armada-xp-gp.dts
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@@ -71,6 +71,27 @@
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};
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};
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+ pcie-controller {
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+ status = "okay";
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+
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+ /*
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+ * The 3 slots are physically present as
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+ * standard PCIe slots on the board.
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+ */
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+ pcie@1,0 {
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+ /* Port 0, Lane 0 */
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+ status = "okay";
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+ };
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+ pcie@9,0 {
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+ /* Port 2, Lane 0 */
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+ status = "okay";
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+ };
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+ pcie@10,0 {
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+ /* Port 3, Lane 0 */
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+ status = "okay";
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+ };
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+ };
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+
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internal-regs {
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serial@12000 {
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clock-frequency = <250000000>;
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@@ -154,27 +175,6 @@
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spi-max-frequency = <108000000>;
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};
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};
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-
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- pcie-controller {
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- status = "okay";
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-
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- /*
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- * The 3 slots are physically present as
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- * standard PCIe slots on the board.
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- */
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- pcie@1,0 {
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- /* Port 0, Lane 0 */
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- status = "okay";
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- };
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- pcie@9,0 {
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- /* Port 2, Lane 0 */
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- status = "okay";
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- };
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- pcie@10,0 {
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- /* Port 3, Lane 0 */
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- status = "okay";
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- };
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- };
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};
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};
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};
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--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
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+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
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@@ -44,6 +44,124 @@
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};
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soc {
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+ /*
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+ * MV78230 has 2 PCIe units Gen2.0: One unit can be
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+ * configured as x4 or quad x1 lanes. One unit is
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+ * x4/x1.
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+ */
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+ pcie-controller {
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+ compatible = "marvell,armada-xp-pcie";
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+ status = "disabled";
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+ device_type = "pci";
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+
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ bus-range = <0x00 0xff>;
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+
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+ ranges =
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+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
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+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
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+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
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+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
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+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
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+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
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+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
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+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
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+ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
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+ 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
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+ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
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+ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
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+ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
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+ 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
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+ 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
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+
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+ pcie@1,0 {
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+ device_type = "pci";
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+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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+ reg = <0x0800 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &mpic 58>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <0>;
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+ clocks = <&gateclk 5>;
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+ status = "disabled";
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+ };
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+
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+ pcie@2,0 {
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+ device_type = "pci";
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+ assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
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+ reg = <0x1000 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &mpic 59>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <1>;
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+ clocks = <&gateclk 6>;
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+ status = "disabled";
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+ };
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+
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+ pcie@3,0 {
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+ device_type = "pci";
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+ assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
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+ reg = <0x1800 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
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+ 0x81000000 0 0 0x81000000 0x3 0 1 0>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &mpic 60>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <2>;
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+ clocks = <&gateclk 7>;
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+ status = "disabled";
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+ };
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+
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+ pcie@4,0 {
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+ device_type = "pci";
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+ assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
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+ reg = <0x2000 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
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+ 0x81000000 0 0 0x81000000 0x4 0 1 0>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &mpic 61>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <3>;
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+ clocks = <&gateclk 8>;
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+ status = "disabled";
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+ };
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+
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+ pcie@9,0 {
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+ device_type = "pci";
|
|
+ assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
|
|
+ reg = <0x4800 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 99>;
|
|
+ marvell,pcie-port = <2>;
|
|
+ marvell,pcie-lane = <0>;
|
|
+ clocks = <&gateclk 26>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
internal-regs {
|
|
pinctrl {
|
|
compatible = "marvell,mv78230-pinctrl";
|
|
@@ -79,108 +197,6 @@
|
|
};
|
|
|
|
/*
|
|
- * MV78230 has 2 PCIe units Gen2.0: One unit can be
|
|
- * configured as x4 or quad x1 lanes. One unit is
|
|
- * x1 only.
|
|
- */
|
|
- pcie-controller {
|
|
- compatible = "marvell,armada-xp-pcie";
|
|
- status = "disabled";
|
|
- device_type = "pci";
|
|
-
|
|
-#address-cells = <3>;
|
|
-#size-cells = <2>;
|
|
-
|
|
- bus-range = <0x00 0xff>;
|
|
-
|
|
- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
|
|
- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
|
|
- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
|
|
- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
|
- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
|
|
- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
|
- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
|
|
-
|
|
- pcie@1,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
|
- reg = <0x0800 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 58>;
|
|
- marvell,pcie-port = <0>;
|
|
- marvell,pcie-lane = <0>;
|
|
- clocks = <&gateclk 5>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@2,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
|
- reg = <0x1000 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 59>;
|
|
- marvell,pcie-port = <0>;
|
|
- marvell,pcie-lane = <1>;
|
|
- clocks = <&gateclk 6>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@3,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
|
- reg = <0x1800 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 60>;
|
|
- marvell,pcie-port = <0>;
|
|
- marvell,pcie-lane = <2>;
|
|
- clocks = <&gateclk 7>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@4,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
|
|
- reg = <0x2000 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 61>;
|
|
- marvell,pcie-port = <0>;
|
|
- marvell,pcie-lane = <3>;
|
|
- clocks = <&gateclk 8>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@5,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
|
- reg = <0x2800 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 62>;
|
|
- marvell,pcie-port = <1>;
|
|
- marvell,pcie-lane = <0>;
|
|
- clocks = <&gateclk 9>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
};
|
|
};
|
|
};
|
|
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
|
|
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
|
|
@@ -45,6 +45,145 @@
|
|
};
|
|
|
|
soc {
|
|
+ /*
|
|
+ * MV78260 has 3 PCIe units Gen2.0: Two units can be
|
|
+ * configured as x4 or quad x1 lanes. One unit is
|
|
+ * x4/x1.
|
|
+ */
|
|
+ pcie-controller {
|
|
+ compatible = "marvell,armada-xp-pcie";
|
|
+ status = "disabled";
|
|
+ device_type = "pci";
|
|
+
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ bus-range = <0x00 0xff>;
|
|
+
|
|
+ ranges =
|
|
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
|
+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
|
+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
|
+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
|
+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
|
+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
|
+ 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
|
|
+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
|
+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
|
+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
|
+ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
|
+ 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
|
+ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
|
+ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
|
+ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
|
+ 0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
|
+ 0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
|
+ 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
|
|
+ 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
|
|
+
|
|
+ pcie@1,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
|
+ reg = <0x0800 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 58>;
|
|
+ marvell,pcie-port = <0>;
|
|
+ marvell,pcie-lane = <0>;
|
|
+ clocks = <&gateclk 5>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@2,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
|
+ reg = <0x1000 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 59>;
|
|
+ marvell,pcie-port = <0>;
|
|
+ marvell,pcie-lane = <1>;
|
|
+ clocks = <&gateclk 6>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@3,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
|
+ reg = <0x1800 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 60>;
|
|
+ marvell,pcie-port = <0>;
|
|
+ marvell,pcie-lane = <2>;
|
|
+ clocks = <&gateclk 7>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@4,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
|
|
+ reg = <0x2000 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 61>;
|
|
+ marvell,pcie-port = <0>;
|
|
+ marvell,pcie-lane = <3>;
|
|
+ clocks = <&gateclk 8>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@9,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
|
|
+ reg = <0x4800 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 99>;
|
|
+ marvell,pcie-port = <2>;
|
|
+ marvell,pcie-lane = <0>;
|
|
+ clocks = <&gateclk 26>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@10,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
|
|
+ reg = <0x5000 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0xa 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 103>;
|
|
+ marvell,pcie-port = <3>;
|
|
+ marvell,pcie-lane = <0>;
|
|
+ clocks = <&gateclk 27>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
internal-regs {
|
|
pinctrl {
|
|
compatible = "marvell,mv78260-pinctrl";
|
|
@@ -98,177 +237,6 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
- /*
|
|
- * MV78260 has 3 PCIe units Gen2.0: Two units can be
|
|
- * configured as x4 or quad x1 lanes. One unit is
|
|
- * x4 only.
|
|
- */
|
|
- pcie-controller {
|
|
- compatible = "marvell,armada-xp-pcie";
|
|
- status = "disabled";
|
|
- device_type = "pci";
|
|
-
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
-
|
|
- bus-range = <0x00 0xff>;
|
|
-
|
|
- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
|
|
- 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
|
|
- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
|
|
- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
|
|
- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
|
- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
|
|
- 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
|
|
- 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
|
|
- 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
|
- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
|
- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
|
|
-
|
|
- pcie@1,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
|
- reg = <0x0800 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 58>;
|
|
- marvell,pcie-port = <0>;
|
|
- marvell,pcie-lane = <0>;
|
|
- clocks = <&gateclk 5>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@2,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
|
- reg = <0x1000 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 59>;
|
|
- marvell,pcie-port = <0>;
|
|
- marvell,pcie-lane = <1>;
|
|
- clocks = <&gateclk 6>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@3,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
|
- reg = <0x1800 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 60>;
|
|
- marvell,pcie-port = <0>;
|
|
- marvell,pcie-lane = <2>;
|
|
- clocks = <&gateclk 7>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@4,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
|
|
- reg = <0x2000 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 61>;
|
|
- marvell,pcie-port = <0>;
|
|
- marvell,pcie-lane = <3>;
|
|
- clocks = <&gateclk 8>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@5,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
|
- reg = <0x2800 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 62>;
|
|
- marvell,pcie-port = <1>;
|
|
- marvell,pcie-lane = <0>;
|
|
- clocks = <&gateclk 9>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@6,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
|
|
- reg = <0x3000 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 63>;
|
|
- marvell,pcie-port = <1>;
|
|
- marvell,pcie-lane = <1>;
|
|
- clocks = <&gateclk 10>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@7,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
|
|
- reg = <0x3800 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 64>;
|
|
- marvell,pcie-port = <1>;
|
|
- marvell,pcie-lane = <2>;
|
|
- clocks = <&gateclk 11>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@8,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
|
|
- reg = <0x4000 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 65>;
|
|
- marvell,pcie-port = <1>;
|
|
- marvell,pcie-lane = <3>;
|
|
- clocks = <&gateclk 12>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@9,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
|
|
- reg = <0x4800 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 99>;
|
|
- marvell,pcie-port = <2>;
|
|
- marvell,pcie-lane = <0>;
|
|
- clocks = <&gateclk 26>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
};
|
|
};
|
|
};
|
|
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
|
|
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
|
|
@@ -60,6 +60,227 @@
|
|
};
|
|
|
|
soc {
|
|
+ /*
|
|
+ * MV78460 has 4 PCIe units Gen2.0: Two units can be
|
|
+ * configured as x4 or quad x1 lanes. Two units are
|
|
+ * x4/x1.
|
|
+ */
|
|
+ pcie-controller {
|
|
+ compatible = "marvell,armada-xp-pcie";
|
|
+ status = "disabled";
|
|
+ device_type = "pci";
|
|
+
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ bus-range = <0x00 0xff>;
|
|
+
|
|
+ ranges =
|
|
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
|
+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
|
+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
|
+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
|
+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
|
+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
|
+ 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
|
|
+ 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
|
+ 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
|
+ 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
|
+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
|
+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
|
+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
|
+ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
|
+ 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
|
+ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
|
+ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
|
+ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
|
+
|
|
+ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
|
+ 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
|
+ 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
|
+ 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
|
+ 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
|
+ 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
|
+ 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
|
+ 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
|
+
|
|
+ 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
|
+ 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
|
|
+
|
|
+ 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
|
|
+ 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
|
|
+
|
|
+ pcie@1,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
|
+ reg = <0x0800 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 58>;
|
|
+ marvell,pcie-port = <0>;
|
|
+ marvell,pcie-lane = <0>;
|
|
+ clocks = <&gateclk 5>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@2,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
|
|
+ reg = <0x1000 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 59>;
|
|
+ marvell,pcie-port = <0>;
|
|
+ marvell,pcie-lane = <1>;
|
|
+ clocks = <&gateclk 6>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@3,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
|
|
+ reg = <0x1800 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 60>;
|
|
+ marvell,pcie-port = <0>;
|
|
+ marvell,pcie-lane = <2>;
|
|
+ clocks = <&gateclk 7>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@4,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
|
|
+ reg = <0x2000 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 61>;
|
|
+ marvell,pcie-port = <0>;
|
|
+ marvell,pcie-lane = <3>;
|
|
+ clocks = <&gateclk 8>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@5,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
|
+ reg = <0x2800 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 62>;
|
|
+ marvell,pcie-port = <1>;
|
|
+ marvell,pcie-lane = <0>;
|
|
+ clocks = <&gateclk 9>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@6,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
|
|
+ reg = <0x3000 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 63>;
|
|
+ marvell,pcie-port = <1>;
|
|
+ marvell,pcie-lane = <1>;
|
|
+ clocks = <&gateclk 10>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@7,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
|
|
+ reg = <0x3800 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x7 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 64>;
|
|
+ marvell,pcie-port = <1>;
|
|
+ marvell,pcie-lane = <2>;
|
|
+ clocks = <&gateclk 11>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@8,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
|
|
+ reg = <0x4000 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x8 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 65>;
|
|
+ marvell,pcie-port = <1>;
|
|
+ marvell,pcie-lane = <3>;
|
|
+ clocks = <&gateclk 12>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@9,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
|
|
+ reg = <0x4800 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 99>;
|
|
+ marvell,pcie-port = <2>;
|
|
+ marvell,pcie-lane = <0>;
|
|
+ clocks = <&gateclk 26>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@10,0 {
|
|
+ device_type = "pci";
|
|
+ assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
|
|
+ reg = <0x5000 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
|
|
+ 0x81000000 0 0 0x81000000 0xa 0 1 0>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &mpic 103>;
|
|
+ marvell,pcie-port = <3>;
|
|
+ marvell,pcie-lane = <0>;
|
|
+ clocks = <&gateclk 27>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
internal-regs {
|
|
pinctrl {
|
|
compatible = "marvell,mv78460-pinctrl";
|
|
@@ -112,194 +333,6 @@
|
|
clocks = <&gateclk 1>;
|
|
status = "disabled";
|
|
};
|
|
-
|
|
- /*
|
|
- * MV78460 has 4 PCIe units Gen2.0: Two units can be
|
|
- * configured as x4 or quad x1 lanes. Two units are
|
|
- * x4/x1.
|
|
- */
|
|
- pcie-controller {
|
|
- compatible = "marvell,armada-xp-pcie";
|
|
- status = "disabled";
|
|
- device_type = "pci";
|
|
-
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
-
|
|
- bus-range = <0x00 0xff>;
|
|
-
|
|
- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
|
|
- 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
|
|
- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
|
|
- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
|
|
- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
|
- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
|
|
- 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
|
|
- 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
|
|
- 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
|
|
- 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
|
- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
|
- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
|
|
-
|
|
- pcie@1,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
|
- reg = <0x0800 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 58>;
|
|
- marvell,pcie-port = <0>;
|
|
- marvell,pcie-lane = <0>;
|
|
- clocks = <&gateclk 5>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@2,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
|
|
- reg = <0x1000 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 59>;
|
|
- marvell,pcie-port = <0>;
|
|
- marvell,pcie-lane = <1>;
|
|
- clocks = <&gateclk 6>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@3,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
|
|
- reg = <0x1800 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 60>;
|
|
- marvell,pcie-port = <0>;
|
|
- marvell,pcie-lane = <2>;
|
|
- clocks = <&gateclk 7>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@4,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
|
|
- reg = <0x2000 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 61>;
|
|
- marvell,pcie-port = <0>;
|
|
- marvell,pcie-lane = <3>;
|
|
- clocks = <&gateclk 8>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@5,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
|
- reg = <0x2800 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 62>;
|
|
- marvell,pcie-port = <1>;
|
|
- marvell,pcie-lane = <0>;
|
|
- clocks = <&gateclk 9>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@6,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
|
|
- reg = <0x3000 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 63>;
|
|
- marvell,pcie-port = <1>;
|
|
- marvell,pcie-lane = <1>;
|
|
- clocks = <&gateclk 10>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@7,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
|
|
- reg = <0x3800 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 64>;
|
|
- marvell,pcie-port = <1>;
|
|
- marvell,pcie-lane = <2>;
|
|
- clocks = <&gateclk 11>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@8,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
|
|
- reg = <0x4000 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 65>;
|
|
- marvell,pcie-port = <1>;
|
|
- marvell,pcie-lane = <3>;
|
|
- clocks = <&gateclk 12>;
|
|
- status = "disabled";
|
|
- };
|
|
- pcie@9,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
|
|
- reg = <0x4800 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 99>;
|
|
- marvell,pcie-port = <2>;
|
|
- marvell,pcie-lane = <0>;
|
|
- clocks = <&gateclk 26>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pcie@10,0 {
|
|
- device_type = "pci";
|
|
- assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
|
|
- reg = <0x5000 0 0 0 0>;
|
|
- #address-cells = <3>;
|
|
- #size-cells = <2>;
|
|
- #interrupt-cells = <1>;
|
|
- ranges;
|
|
- interrupt-map-mask = <0 0 0 0>;
|
|
- interrupt-map = <0 0 0 0 &mpic 103>;
|
|
- marvell,pcie-port = <3>;
|
|
- marvell,pcie-lane = <0>;
|
|
- clocks = <&gateclk 27>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
};
|
|
};
|
|
};
|
|
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
|
|
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
|
|
@@ -59,6 +59,15 @@
|
|
};
|
|
};
|
|
|
|
+ pcie-controller {
|
|
+ status = "okay";
|
|
+ /* Internal mini-PCIe connector */
|
|
+ pcie@1,0 {
|
|
+ /* Port 0, Lane 0 */
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
internal-regs {
|
|
serial@12000 {
|
|
clock-frequency = <250000000>;
|
|
@@ -172,15 +181,6 @@
|
|
usb@51000 {
|
|
status = "okay";
|
|
};
|
|
-
|
|
- pcie-controller {
|
|
- status = "okay";
|
|
- /* Internal mini-PCIe connector */
|
|
- pcie@1,0 {
|
|
- /* Port 0, Lane 0 */
|
|
- status = "okay";
|
|
- };
|
|
- };
|
|
};
|
|
};
|
|
};
|