openwrt-owl/target
Felix Fietkau c75a0e86b1 ar71xx: add mask and shift for RXD/RDV bits in AR934X register file
The commit r38948 ("ag71xx: add F1E specific feature bit definitions to AR934X
register file") introduced definitions for some bits in the RDV/RXD part of the
ETH_CFG register of AR934x. These are incomplete because ETH_RXDV_DELAY is
specified as 17:16 and ETH_RXD_DELAY is specified 15:14. The original commit
only specified the lower bits. The upper bits also have to be unset when the
lower bits should only be set.

Signed-off-by: Sven Eckelmann <sven@open-mesh.com>

SVN-Revision: 45522
2015-04-20 15:00:41 +00:00
..
imagebuilder imagebuilder: align filename with SDK 2015-02-07 21:01:48 +00:00
linux ar71xx: add mask and shift for RXD/RDV bits in AR934X register file 2015-04-20 15:00:41 +00:00
sdk sdk: use prepare target to initialize git snapshot 2015-02-08 22:54:27 +00:00
toolchain toolchain: respect CONFIG_VERSION_FILENAMES and add host system suffix 2015-02-07 21:01:37 +00:00
Config.in build: remove obsolete references to cris and avr32 2015-03-24 10:07:40 +00:00
Makefile