mirror of https://github.com/hak5/openwrt-owl.git
180 lines
5.5 KiB
C
180 lines
5.5 KiB
C
#ifndef __MTK_PHY_NEW_H
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#define __MTK_PHY_NEW_H
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//#define CONFIG_U3D_HAL_SUPPORT
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/* include system library */
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#include <linux/gfp.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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/* Choose PHY R/W implementation */
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//#define CONFIG_U3_PHY_GPIO_SUPPORT //SW I2C implemented by GPIO
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#define CONFIG_U3_PHY_AHB_SUPPORT //AHB, only on SoC
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/* Choose PHY version */
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//Select your project by defining one of the followings
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#define CONFIG_PROJECT_7621 //7621
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#define CONFIG_PROJECT_PHY
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/* BASE ADDRESS DEFINE, should define this on ASIC */
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#define PHY_BASE 0xBE1D0000
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#define SIFSLV_FM_FEG_BASE (PHY_BASE+0x100)
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#define SIFSLV_CHIP_BASE (PHY_BASE+0x700)
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#define U2_PHY_BASE (PHY_BASE+0x800)
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#define U3_PHYD_BASE (PHY_BASE+0x900)
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#define U3_PHYD_B2_BASE (PHY_BASE+0xa00)
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#define U3_PHYA_BASE (PHY_BASE+0xb00)
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#define U3_PHYA_DA_BASE (PHY_BASE+0xc00)
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#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
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#define SIFSLV_FM_FEG_BASE_P1 (PHY_BASE+0x100)
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#define SIFSLV_CHIP_BASE_P1 (PHY_BASE+0x700)
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#define U2_PHY_BASE_P1 (PHY_BASE+0x1000)
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#define U3_PHYD_BASE_P1 (PHY_BASE+0x1100)
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#define U3_PHYD_B2_BASE_P1 (PHY_BASE+0x1200)
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#define U3_PHYA_BASE_P1 (PHY_BASE+0x1300)
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#define U3_PHYA_DA_BASE_P1 (PHY_BASE+0x1400)
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#endif
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/*
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0x00000100 MODULE ssusb_sifslv_fmreg ssusb_sifslv_fmreg
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0x00000700 MODULE ssusb_sifslv_ippc ssusb_sifslv_ippc
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0x00000800 MODULE ssusb_sifslv_u2phy_com ssusb_sifslv_u2_phy_com_T28
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0x00000900 MODULE ssusb_sifslv_u3phyd ssusb_sifslv_u3phyd_T28
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0x00000a00 MODULE ssusb_sifslv_u3phyd_bank2 ssusb_sifslv_u3phyd_bank2_T28
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0x00000b00 MODULE ssusb_sifslv_u3phya ssusb_sifslv_u3phya_T28
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0x00000c00 MODULE ssusb_sifslv_u3phya_da ssusb_sifslv_u3phya_da_T28
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*/
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/* TYPE DEFINE */
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typedef unsigned int PHY_UINT32;
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typedef int PHY_INT32;
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typedef unsigned short PHY_UINT16;
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typedef short PHY_INT16;
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typedef unsigned char PHY_UINT8;
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typedef char PHY_INT8;
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typedef PHY_UINT32 __bitwise PHY_LE32;
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/* CONSTANT DEFINE */
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#define PHY_FALSE 0
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#define PHY_TRUE 1
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/* MACRO DEFINE */
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#define DRV_WriteReg32(addr,data) ((*(volatile PHY_UINT32 *)(addr)) = (unsigned long)(data))
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#define DRV_Reg32(addr) (*(volatile PHY_UINT32 *)(addr))
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#define DRV_MDELAY mdelay
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#define DRV_MSLEEP msleep
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#define DRV_UDELAY udelay
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#define DRV_USLEEP usleep
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/* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
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PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data);
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PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr);
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PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data);
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PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr);
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/* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
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PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
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PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
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PHY_INT32 U3PhyReadField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
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PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
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struct u3phy_info {
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PHY_INT32 phy_version;
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PHY_INT32 phyd_version_addr;
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#ifdef CONFIG_PROJECT_PHY
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struct u2phy_reg *u2phy_regs;
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struct u3phya_reg *u3phya_regs;
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struct u3phya_da_reg *u3phya_da_regs;
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struct u3phyd_reg *u3phyd_regs;
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struct u3phyd_bank2_reg *u3phyd_bank2_regs;
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struct sifslv_chip_reg *sifslv_chip_regs;
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struct sifslv_fm_feg *sifslv_fm_regs;
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#endif
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};
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struct u3phy_operator {
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PHY_INT32 (*init) (struct u3phy_info *info);
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PHY_INT32 (*change_pipe_phase) (struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
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PHY_INT32 (*eyescan_init) (struct u3phy_info *info);
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PHY_INT32 (*eyescan) (struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
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PHY_INT32 (*u2_save_current_entry) (struct u3phy_info *info);
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PHY_INT32 (*u2_save_current_recovery) (struct u3phy_info *info);
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PHY_INT32 (*u2_slew_rate_calibration) (struct u3phy_info *info);
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};
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#ifdef U3_PHY_LIB
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#define AUTOEXT
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#else
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#define AUTOEXT extern
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#endif
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AUTOEXT struct u3phy_info *u3phy;
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AUTOEXT struct u3phy_info *u3phy_p1;
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AUTOEXT struct u3phy_operator *u3phy_ops;
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/*********eye scan required*********/
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#define LO_BYTE(x) ((PHY_UINT8)((x) & 0xFF))
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#define HI_BYTE(x) ((PHY_UINT8)(((x) & 0xFF00) >> 8))
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typedef enum
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{
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SCAN_UP,
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SCAN_DN
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} enumScanDir;
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struct strucScanRegion
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{
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PHY_INT8 bX_tl;
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PHY_INT8 bY_tl;
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PHY_INT8 bX_br;
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PHY_INT8 bY_br;
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PHY_INT8 bDeltaX;
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PHY_INT8 bDeltaY;
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};
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struct strucTestCycle
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{
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PHY_UINT16 wEyeCnt;
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PHY_INT8 bNumOfEyeCnt;
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PHY_INT8 bPICalEn;
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PHY_INT8 bNumOfIgnoreCnt;
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};
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#define ERRCNT_MAX 128
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#define CYCLE_COUNT_MAX 15
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/// the map resolution is 128 x 128 pts
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#define MAX_X 127
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#define MAX_Y 127
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#define MIN_X 0
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#define MIN_Y 0
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PHY_INT32 u3phy_init(void);
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AUTOEXT struct strucScanRegion _rEye1;
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AUTOEXT struct strucScanRegion _rEye2;
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AUTOEXT struct strucTestCycle _rTestCycle;
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AUTOEXT PHY_UINT8 _bXcurr;
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AUTOEXT PHY_UINT8 _bYcurr;
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AUTOEXT enumScanDir _eScanDir;
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AUTOEXT PHY_INT8 _fgXChged;
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AUTOEXT PHY_INT8 _bPIResult;
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/* use local variable instead to save memory use */
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#if 0
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AUTOEXT PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
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AUTOEXT PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
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#endif
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/***********************************/
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#endif
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