mirror of https://github.com/hak5/openwrt-owl.git
111 lines
3.1 KiB
Diff
111 lines
3.1 KiB
Diff
From: Felix Fietkau <nbd@nbd.name>
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Date: Tue, 6 Mar 2018 13:22:43 +0100
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Subject: [PATCH] MIPS: ath79: move legacy "wdt" and "uart" clock aliases
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out of soc init
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Preparation for reusing functions for DT
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -109,9 +109,6 @@ static void __init ar71xx_clocks_init(vo
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ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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-
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- clk_add_alias("wdt", NULL, "ahb", NULL);
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- clk_add_alias("uart", NULL, "ahb", NULL);
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}
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static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
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@@ -139,9 +136,6 @@ static void __init ar724x_clocks_init(vo
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ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
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ar724x_clk_init(ref_clk, ath79_pll_base);
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-
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- clk_add_alias("wdt", NULL, "ahb", NULL);
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- clk_add_alias("uart", NULL, "ahb", NULL);
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}
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static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
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@@ -217,9 +211,6 @@ static void __init ar933x_clocks_init(vo
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ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
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ar9330_clk_init(ref_clk, ath79_pll_base);
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-
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- clk_add_alias("wdt", NULL, "ahb", NULL);
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- clk_add_alias("uart", NULL, "ref", NULL);
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}
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static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
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@@ -352,9 +343,6 @@ static void __init ar934x_clocks_init(vo
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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- clk_add_alias("wdt", NULL, "ref", NULL);
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- clk_add_alias("uart", NULL, "ref", NULL);
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-
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iounmap(dpll_base);
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}
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@@ -438,9 +426,6 @@ static void __init qca953x_clocks_init(v
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ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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-
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- clk_add_alias("wdt", NULL, "ref", NULL);
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- clk_add_alias("uart", NULL, "ref", NULL);
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}
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static void __init qca955x_clocks_init(void)
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@@ -523,9 +508,6 @@ static void __init qca955x_clocks_init(v
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ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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-
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- clk_add_alias("wdt", NULL, "ref", NULL);
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- clk_add_alias("uart", NULL, "ref", NULL);
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}
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static void __init qca956x_clocks_init(void)
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@@ -617,13 +599,13 @@ static void __init qca956x_clocks_init(v
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ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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-
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- clk_add_alias("wdt", NULL, "ref", NULL);
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- clk_add_alias("uart", NULL, "ref", NULL);
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}
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void __init ath79_clocks_init(void)
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{
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+ const char *wdt;
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+ const char *uart;
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+
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if (soc_is_ar71xx())
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ar71xx_clocks_init();
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else if (soc_is_ar724x() || soc_is_ar913x())
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@@ -640,6 +622,20 @@ void __init ath79_clocks_init(void)
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qca956x_clocks_init();
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else
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BUG();
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+
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+ if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
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+ wdt = "ahb";
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+ uart = "ahb";
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+ } else if (soc_is_ar933x()) {
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+ wdt = "ahb";
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+ uart = "ref";
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+ } else {
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+ wdt = "ref";
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+ uart = "ref";
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+ }
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+
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+ clk_add_alias("wdt", NULL, wdt, NULL);
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+ clk_add_alias("uart", NULL, uart, NULL);
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}
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unsigned long __init
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