mirror of https://github.com/hak5/openwrt-owl.git
390 lines
11 KiB
Diff
390 lines
11 KiB
Diff
--- a/arch/arm/Kconfig
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+++ b/arch/arm/Kconfig
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@@ -400,6 +400,7 @@ config ARCH_GEMINI
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select CLKSRC_MMIO
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select CPU_FA526
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select GENERIC_CLOCKEVENTS
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+ select MIGHT_HAVE_PCI
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help
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Support for the Cortina Systems Gemini family SoCs
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--- a/arch/arm/mach-gemini/include/mach/hardware.h
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+++ b/arch/arm/mach-gemini/include/mach/hardware.h
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@@ -71,4 +71,9 @@
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*/
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#define IO_ADDRESS(x) IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
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+/*
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+ * PCI subsystem macros
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+ */
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+#define pcibios_assign_all_busses() 1
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+
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#endif
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--- a/arch/arm/mach-gemini/include/mach/irqs.h
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+++ b/arch/arm/mach-gemini/include/mach/irqs.h
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@@ -43,11 +43,14 @@
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#define NORMAL_IRQ_NUM 32
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-#define GPIO_IRQ_BASE NORMAL_IRQ_NUM
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+#define PCI_IRQ_BASE NORMAL_IRQ_NUM
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+#define PCI_IRQ_NUM 4
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+
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+#define GPIO_IRQ_BASE (NORMAL_IRQ_NUM + PCI_IRQ_NUM)
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#define GPIO_IRQ_NUM (3 * 32)
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#define ARCH_TIMER_IRQ IRQ_TIMER2
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-#define NR_IRQS (NORMAL_IRQ_NUM + GPIO_IRQ_NUM)
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+#define NR_IRQS (NORMAL_IRQ_NUM + PCI_IRQ_NUM + GPIO_IRQ_NUM)
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#endif /* __MACH_IRQS_H__ */
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--- a/arch/arm/mach-gemini/Makefile
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+++ b/arch/arm/mach-gemini/Makefile
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@@ -6,6 +6,8 @@
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obj-y := irq.o mm.o time.o devices.o gpio.o idle.o reset.o
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+obj-$(CONFIG_PCI) += pci.o
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+
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# Board-specific support
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obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o
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obj-$(CONFIG_MACH_RUT100) += board-rut1xx.o
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--- a/arch/arm/mach-gemini/mm.c
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+++ b/arch/arm/mach-gemini/mm.c
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@@ -59,6 +59,11 @@ static struct map_desc gemini_io_desc[]
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.length = SZ_512K,
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.type = MT_DEVICE,
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}, {
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+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_PCI_IO_BASE),
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+ .pfn = __phys_to_pfn(GEMINI_PCI_IO_BASE),
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+ .length = SZ_512K,
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+ .type = MT_DEVICE,
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+ }, {
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.virtual = (unsigned long)IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
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.pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE),
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.length = SZ_512K,
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--- /dev/null
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+++ b/arch/arm/mach-gemini/pci.c
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@@ -0,0 +1,320 @@
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+/*
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+ * Support for Gemini PCI Controller
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+ *
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+ * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
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+ * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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+ *
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+ * based on SL2312 PCI controller code
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+ * Storlink (C) 2003
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/pci.h>
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+#include <linux/irq.h>
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+#include <linux/gpio.h>
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+
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+#include <asm/mach/pci.h>
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+
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+#include <mach/irqs.h>
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+#include <mach/hardware.h>
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+
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+#define GEMINI_PCI_IOSIZE_1M 0x0000
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+
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+#define GEMINI_PCI_PMC 0x40
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+#define GEMINI_PCI_PMCSR 0x44
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+#define GEMINI_PCI_CTRL1 0x48
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+#define GEMINI_PCI_CTRL2 0x4C
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+#define GEMINI_PCI_MEM1_BASE_SIZE 0x50
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+#define GEMINI_PCI_MEM2_BASE_SIZE 0x54
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+#define GEMINI_PCI_MEM3_BASE_SIZE 0x58
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+
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+#define PCI_CTRL2_INTSTS_OFFSET 28
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+#define PCI_CTRL2_INTMASK_OFFSET 22
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+
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+#define GEMINI_PCI_DMA_MASK 0xFFF00000
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+#define GEMINI_PCI_DMA_MEM1_BASE 0x00000000
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+#define GEMINI_PCI_DMA_MEM2_BASE 0x00000000
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+#define GEMINI_PCI_DMA_MEM3_BASE 0x00000000
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+#define GEMINI_PCI_DMA_MEM1_SIZE 7
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+#define GEMINI_PCI_DMA_MEM2_SIZE 6
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+#define GEMINI_PCI_DMA_MEM3_SIZE 6
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+
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+#define PCI_CONF_ENABLE (1 << 31)
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+#define PCI_CONF_WHERE(r) ((r) & 0xFC)
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+#define PCI_CONF_BUS(b) (((b) & 0xFF) << 16)
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+#define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11)
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+#define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8)
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+
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+#define PCI_IOSIZE_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE))
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+#define PCI_PROT_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x04)
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+#define PCI_CTRL_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x08)
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+#define PCI_SOFTRST_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x10)
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+#define PCI_CONFIG_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x28)
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+#define PCI_DATA_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x2C)
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+
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+
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+static DEFINE_SPINLOCK(gemini_pci_lock);
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+
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+static int gemini_pci_read_config(struct pci_bus* bus, unsigned int fn,
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+ int config, int size, u32* value)
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+{
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+ unsigned long irq_flags;
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+
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+ spin_lock_irqsave(&gemini_pci_lock, irq_flags);
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+
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+ __raw_writel(PCI_CONF_BUS(bus->number) |
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+ PCI_CONF_DEVICE(PCI_SLOT(fn)) |
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+ PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
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+ PCI_CONF_WHERE(config) |
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+ PCI_CONF_ENABLE,
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+ PCI_CONFIG_REG);
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+
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+ *value = __raw_readl(PCI_DATA_REG);
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+
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+ if (size == 1)
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+ *value = (*value >> (8 * (config & 3))) & 0xFF;
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+ else if (size == 2)
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+ *value = (*value >> (8 * (config & 3))) & 0xFFFF;
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+
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+ spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
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+
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+ dev_dbg(&bus->dev,
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+ "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
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+ PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+static int gemini_pci_write_config(struct pci_bus* bus, unsigned int fn,
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+ int config, int size, u32 value)
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+{
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+ unsigned long irq_flags = 0;
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+ int ret = PCIBIOS_SUCCESSFUL;
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+
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+ dev_dbg(&bus->dev,
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+ "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
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+ PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
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+
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+ spin_lock_irqsave(&gemini_pci_lock, irq_flags);
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+
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+ __raw_writel(PCI_CONF_BUS(bus->number) |
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+ PCI_CONF_DEVICE(PCI_SLOT(fn)) |
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+ PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
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+ PCI_CONF_WHERE(config) |
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+ PCI_CONF_ENABLE,
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+ PCI_CONFIG_REG);
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+
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+ switch(size) {
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+ case 4:
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+ __raw_writel(value, PCI_DATA_REG);
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+ break;
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+ case 2:
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+ __raw_writew(value, PCI_DATA_REG + (config & 3));
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+ break;
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+ case 1:
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+ __raw_writeb(value, PCI_DATA_REG + (config & 3));
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+ break;
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+ default:
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+ ret = PCIBIOS_BAD_REGISTER_NUMBER;
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+ }
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+
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+ spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
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+
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+ return ret;
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+}
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+
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+static struct pci_ops gemini_pci_ops = {
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+ .read = gemini_pci_read_config,
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+ .write = gemini_pci_write_config,
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+};
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+
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+static struct resource gemini_pci_resource_io = {
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+ .name = "PCI I/O Space",
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+ .start = GEMINI_PCI_IO_BASE,
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+ .end = GEMINI_PCI_IO_BASE + SZ_1M - 1,
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+ .flags = IORESOURCE_IO,
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+};
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+
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+static struct resource gemini_pci_resource_mem = {
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+ .name = "PCI Memory Space",
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+ .start = GEMINI_PCI_MEM_BASE,
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+ .end = GEMINI_PCI_MEM_BASE + SZ_128M - 1,
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+static int __init gemini_pci_request_resources(struct pci_sys_data *sys)
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+{
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+ if (request_resource(&ioport_resource, &gemini_pci_resource_io))
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+ goto bad_resources;
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+ if (request_resource(&iomem_resource, &gemini_pci_resource_mem))
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+ goto bad_resources;
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+
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+ pci_add_resource(&sys->resources, &gemini_pci_resource_io);
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+ pci_add_resource(&sys->resources, &gemini_pci_resource_mem);
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+
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+ return 0;
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+
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+bad_resources:
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+ pr_err("Gemini PCI: request_resource() failed. "
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+ "Abort PCI bus enumeration.\n");
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+ return -1;
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+}
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+
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+static int __init gemini_pci_setup(int nr, struct pci_sys_data *sys)
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+{
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+ unsigned int cmd;
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+
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+ pcibios_min_io = 0x100;
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+ pcibios_min_mem = 0;
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+
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+ if ((nr > 0) || gemini_pci_request_resources(sys))
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+ return 0;
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+
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+ /* setup I/O space to 1MB size */
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+ __raw_writel(GEMINI_PCI_IOSIZE_1M, PCI_IOSIZE_REG);
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+
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+ /* setup hostbridge */
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+ cmd = __raw_readl(PCI_CTRL_REG);
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+ cmd |= PCI_COMMAND_IO;
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+ cmd |= PCI_COMMAND_MEMORY;
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+ cmd |= PCI_COMMAND_MASTER;
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+ __raw_writel(cmd, PCI_CTRL_REG);
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+
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+ return 1;
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+}
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+
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+static struct pci_bus* __init gemini_pci_scan_bus(int nr, struct pci_sys_data* sys)
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+{
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+ unsigned int reg = 0;
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+ struct pci_bus* bus = 0;
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+
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+ bus = pci_scan_bus(nr, &gemini_pci_ops, sys);
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+ if (bus) {
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+ dev_dbg(&bus->dev, "setting up PCI DMA\n");
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+ reg = (GEMINI_PCI_DMA_MEM1_BASE & GEMINI_PCI_DMA_MASK)
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+ | (GEMINI_PCI_DMA_MEM1_SIZE << 16);
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+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM1_BASE_SIZE, 4, reg);
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+ reg = (GEMINI_PCI_DMA_MEM2_BASE & GEMINI_PCI_DMA_MASK)
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+ | (GEMINI_PCI_DMA_MEM2_SIZE << 16);
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+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM2_BASE_SIZE, 4, reg);
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+ reg = (GEMINI_PCI_DMA_MEM3_BASE & GEMINI_PCI_DMA_MASK)
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+ | (GEMINI_PCI_DMA_MEM3_SIZE << 16);
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+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM3_BASE_SIZE, 4, reg);
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+ }
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+
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+ return bus;
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+}
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+
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+/* Should work with all boards based on original Storlink EVB */
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+static int __init gemini_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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+{
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+ if (slot < 9 || slot > 12)
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+ return -1;
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+
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+ return PCI_IRQ_BASE + (((slot - 9) + (pin - 1)) & 0x3);
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+}
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+
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+static struct hw_pci gemini_hw_pci __initdata = {
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+ .nr_controllers = 1,
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+ .setup = gemini_pci_setup,
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+ .scan = gemini_pci_scan_bus,
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+ .map_irq = gemini_pci_map_irq,
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+};
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+
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+/* we need this for muxed PCI interrupts handling */
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+static struct pci_bus bogus_pci_bus;
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+
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+static void gemini_pci_ack_irq(struct irq_data *d)
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+{
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+ unsigned int irq = d->irq;
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+ unsigned int reg;
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+
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+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
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+ reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
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+ reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTSTS_OFFSET);
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+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
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+}
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+
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+static void gemini_pci_mask_irq(struct irq_data *d)
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+{
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+ unsigned int irq = d->irq;
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+ unsigned int reg;
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+
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+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
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+ reg &= ~((0xF << PCI_CTRL2_INTSTS_OFFSET)
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+ | (1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET)));
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+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
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+}
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+
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+static void gemini_pci_unmask_irq(struct irq_data *d)
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+{
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+ unsigned int irq = d->irq;
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+ unsigned int reg;
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+
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+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
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+ reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
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+ reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET);
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+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
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+}
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+
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+static void gemini_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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+{
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+ unsigned int pci_irq_no, irq_stat, reg, i;
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+
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+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
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+ irq_stat = reg >> PCI_CTRL2_INTSTS_OFFSET;
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+
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+ for (i = 0; i < 4; i++) {
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+
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+ if ((irq_stat & (1 << i)) == 0)
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+ continue;
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+
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+ pci_irq_no = PCI_IRQ_BASE + i;
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+
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+ BUG_ON(!(irq_desc[pci_irq_no].handle_irq));
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+ irq_desc[pci_irq_no].handle_irq(pci_irq_no,
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+ &irq_desc[pci_irq_no]);
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+ }
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+}
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+
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+static struct irq_chip gemini_pci_irq_chip = {
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+ .name = "PCI",
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+ .irq_ack = gemini_pci_ack_irq,
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+ .irq_mask = gemini_pci_mask_irq,
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+ .irq_unmask = gemini_pci_unmask_irq,
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+};
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+
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+static int __init gemini_pci_init(void)
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+{
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+ int i;
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+
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+ for (i = 72; i <= 95; i++)
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+ gpio_request(i, "PCI");
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+
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+ /* initialize our bogus bus */
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+ dev_set_name(&bogus_pci_bus.dev, "PCI IRQ handler");
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+ bogus_pci_bus.number = 0;
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+
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+ /* mask and clear all interrupts */
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+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2 + 2, 2,
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+ 0xF000);
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+
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+ for (i = PCI_IRQ_BASE; i < PCI_IRQ_BASE + 4; i++) {
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+ irq_set_chip_and_handler(i, &gemini_pci_irq_chip,
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+ handle_level_irq);
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+ set_irq_flags(i, IRQF_VALID);
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+ }
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+
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+ irq_set_chained_handler(IRQ_PCI, gemini_pci_irq_handler);
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+
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+ pci_common_init(&gemini_hw_pci);
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+
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+ return 0;
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+}
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+
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+subsys_initcall(gemini_pci_init);
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