mirror of https://github.com/hak5/openwrt-owl.git
191 lines
5.6 KiB
Diff
191 lines
5.6 KiB
Diff
From 63ecfef8560631a15ee13129b2778cd4dffbcfe2 Mon Sep 17 00:00:00 2001
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From: Stephen Boyd <sboyd@codeaurora.org>
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Date: Wed, 18 Jun 2014 14:18:31 -0700
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Subject: [PATCH 169/182] clk: qcom: Add support for Krait clocks
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The Krait clocks are made up of a series of muxes and a divider
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that choose between a fixed rate clock and dedicated HFPLLs for
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each CPU. Instead of using mmio accesses to remux parents, the
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Krait implementation exposes the remux control via cp15
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registers. Support these clocks.
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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drivers/clk/qcom/Kconfig | 4 ++
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drivers/clk/qcom/Makefile | 1 +
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drivers/clk/qcom/clk-krait.c | 121 ++++++++++++++++++++++++++++++++++++++++++
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drivers/clk/qcom/clk-krait.h | 22 ++++++++
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4 files changed, 148 insertions(+)
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create mode 100644 drivers/clk/qcom/clk-krait.c
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create mode 100644 drivers/clk/qcom/clk-krait.h
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--- a/drivers/clk/qcom/Kconfig
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+++ b/drivers/clk/qcom/Kconfig
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@@ -61,3 +61,7 @@ config QCOM_HFPLL
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Support for the high-frequency PLLs present on Qualcomm devices.
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Say Y if you want to support CPU frequency scaling on devices
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such as MSM8974, APQ8084, etc.
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+
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+config KRAIT_CLOCKS
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+ bool
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+ select KRAIT_L2_ACCESSORS
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--- a/drivers/clk/qcom/Makefile
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+++ b/drivers/clk/qcom/Makefile
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@@ -7,6 +7,7 @@ clk-qcom-y += clk-rcg.o
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clk-qcom-y += clk-rcg2.o
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clk-qcom-y += clk-branch.o
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clk-qcom-y += clk-generic.o
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+clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
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clk-qcom-y += clk-hfpll.o
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clk-qcom-y += reset.o
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--- /dev/null
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+++ b/drivers/clk/qcom/clk-krait.c
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@@ -0,0 +1,121 @@
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+/*
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+ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/delay.h>
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+#include <linux/err.h>
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+#include <linux/clk-provider.h>
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+#include <linux/spinlock.h>
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+
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+#include <asm/krait-l2-accessors.h>
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+
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+#include "clk-krait.h"
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+
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+/* Secondary and primary muxes share the same cp15 register */
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+static DEFINE_SPINLOCK(kpss_clock_reg_lock);
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+
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+#define LPL_SHIFT 8
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+static void __kpss_mux_set_sel(struct mux_clk *mux, int sel)
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+{
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+ unsigned long flags;
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+ u32 regval;
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+
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+ spin_lock_irqsave(&kpss_clock_reg_lock, flags);
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+ regval = krait_get_l2_indirect_reg(mux->offset);
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+ regval &= ~(mux->mask << mux->shift);
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+ regval |= (sel & mux->mask) << mux->shift;
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+ if (mux->priv) {
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+ regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
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+ regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
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+ }
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+ krait_set_l2_indirect_reg(mux->offset, regval);
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+ spin_unlock_irqrestore(&kpss_clock_reg_lock, flags);
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+
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+ /* Wait for switch to complete. */
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+ mb();
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+ udelay(1);
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+}
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+
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+static int kpss_mux_set_sel(struct mux_clk *mux, int sel)
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+{
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+ mux->en_mask = sel;
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+ /* Don't touch mux if CPU is off as it won't work */
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+ if (__clk_is_enabled(mux->hw.clk))
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+ __kpss_mux_set_sel(mux, sel);
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+ return 0;
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+}
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+
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+static int kpss_mux_get_sel(struct mux_clk *mux)
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+{
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+ u32 sel;
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+
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+ sel = krait_get_l2_indirect_reg(mux->offset);
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+ sel >>= mux->shift;
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+ sel &= mux->mask;
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+ mux->en_mask = sel;
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+
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+ return sel;
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+}
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+
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+static int kpss_mux_enable(struct mux_clk *mux)
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+{
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+ __kpss_mux_set_sel(mux, mux->en_mask);
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+ return 0;
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+}
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+
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+static void kpss_mux_disable(struct mux_clk *mux)
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+{
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+ __kpss_mux_set_sel(mux, mux->safe_sel);
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+}
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+
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+const struct clk_mux_ops clk_mux_ops_kpss = {
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+ .enable = kpss_mux_enable,
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+ .disable = kpss_mux_disable,
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+ .set_mux_sel = kpss_mux_set_sel,
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+ .get_mux_sel = kpss_mux_get_sel,
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+};
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+EXPORT_SYMBOL_GPL(clk_mux_ops_kpss);
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+
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+/*
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+ * The divider can divide by 2, 4, 6 and 8. But we only really need div-2. So
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+ * force it to div-2 during handoff and treat it like a fixed div-2 clock.
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+ */
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+static int kpss_div2_get_div(struct div_clk *div)
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+{
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+ unsigned long flags;
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+ u32 regval;
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+ int val;
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+
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+ spin_lock_irqsave(&kpss_clock_reg_lock, flags);
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+ regval = krait_get_l2_indirect_reg(div->offset);
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+ val = (regval >> div->shift) & div->mask;
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+ regval &= ~(div->mask << div->shift);
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+ if (div->priv)
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+ regval &= ~(div->mask << (div->shift + LPL_SHIFT));
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+ krait_set_l2_indirect_reg(div->offset, regval);
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+ spin_unlock_irqrestore(&kpss_clock_reg_lock, flags);
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+
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+ val = (val + 1) * 2;
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+ WARN(val != 2, "Divider %s was configured to div-%d instead of 2!\n",
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+ __clk_get_name(div->hw.clk), val);
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+
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+ return 2;
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+}
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+
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+const struct clk_div_ops clk_div_ops_kpss_div2 = {
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+ .get_div = kpss_div2_get_div,
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+};
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+EXPORT_SYMBOL_GPL(clk_div_ops_kpss_div2);
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--- /dev/null
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+++ b/drivers/clk/qcom/clk-krait.h
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@@ -0,0 +1,22 @@
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+/*
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+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#ifndef __SOC_QCOM_CLOCK_KRAIT_H
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+#define __SOC_QCOM_CLOCK_KRAIT_H
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+
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+#include <linux/clk/msm-clk-generic.h>
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+
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+extern const struct clk_mux_ops clk_mux_ops_kpss;
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+extern const struct clk_div_ops clk_div_ops_kpss_div2;
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+
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+#endif
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