mirror of https://github.com/hak5/openwrt-owl.git
255 lines
7.0 KiB
Diff
255 lines
7.0 KiB
Diff
From 4ccbe584ecb970f86bab58c0ca93998cccc9e810 Mon Sep 17 00:00:00 2001
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From: Stephen Boyd <sboyd@codeaurora.org>
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Date: Fri, 16 May 2014 16:07:12 -0700
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Subject: [PATCH 106/182] clk: qcom: Properly support display clocks on
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msm8974
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The display clocks all source from dedicated phy PLLs within their
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respective multimedia hardware block. Hook up these PLLs to the
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display clocks with the appropriate parent mappings, clock flags,
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and the appropriate clock ops. This should allow the display
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clocks to work once the appropriate phy PLL driver registers their
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PLL clocks.
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Mike Turquette <mturquette@linaro.org>
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---
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drivers/clk/qcom/mmcc-msm8974.c | 105 ++++++++++++++++++++-------------------
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1 file changed, 54 insertions(+), 51 deletions(-)
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--- a/drivers/clk/qcom/mmcc-msm8974.c
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+++ b/drivers/clk/qcom/mmcc-msm8974.c
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@@ -41,9 +41,11 @@
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#define P_EDPVCO 3
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#define P_GPLL1 4
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#define P_DSI0PLL 4
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+#define P_DSI0PLL_BYTE 4
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#define P_MMPLL2 4
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#define P_MMPLL3 4
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#define P_DSI1PLL 5
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+#define P_DSI1PLL_BYTE 5
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static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
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[P_XO] = 0,
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@@ -161,6 +163,24 @@ static const char *mmcc_xo_dsi_hdmi_edp_
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"dsi1pll",
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};
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+static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
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+ [P_XO] = 0,
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+ [P_EDPLINK] = 4,
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+ [P_HDMIPLL] = 3,
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+ [P_GPLL0] = 5,
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+ [P_DSI0PLL_BYTE] = 1,
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+ [P_DSI1PLL_BYTE] = 2,
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+};
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+
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+static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
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+ "xo",
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+ "edp_link_clk",
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+ "hdmipll",
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+ "gpll0_vote",
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+ "dsi0pllbyte",
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+ "dsi1pllbyte",
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+};
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+
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#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
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static struct clk_pll mmpll0 = {
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@@ -500,15 +520,8 @@ static struct clk_rcg2 jpeg2_clk_src = {
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},
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};
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-static struct freq_tbl ftbl_mdss_pclk0_clk[] = {
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- F(125000000, P_DSI0PLL, 2, 0, 0),
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- F(250000000, P_DSI0PLL, 1, 0, 0),
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- { }
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-};
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-
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-static struct freq_tbl ftbl_mdss_pclk1_clk[] = {
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- F(125000000, P_DSI1PLL, 2, 0, 0),
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- F(250000000, P_DSI1PLL, 1, 0, 0),
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+static struct freq_tbl pixel_freq_tbl[] = {
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+ { .src = P_DSI0PLL },
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{ }
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};
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@@ -517,12 +530,13 @@ static struct clk_rcg2 pclk0_clk_src = {
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
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- .freq_tbl = ftbl_mdss_pclk0_clk,
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+ .freq_tbl = pixel_freq_tbl,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pclk0_clk_src",
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.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
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.num_parents = 6,
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- .ops = &clk_rcg2_ops,
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+ .ops = &clk_pixel_ops,
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+ .flags = CLK_SET_RATE_PARENT,
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},
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};
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@@ -531,12 +545,13 @@ static struct clk_rcg2 pclk1_clk_src = {
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
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- .freq_tbl = ftbl_mdss_pclk1_clk,
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+ .freq_tbl = pixel_freq_tbl,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pclk1_clk_src",
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.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
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.num_parents = 6,
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- .ops = &clk_rcg2_ops,
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+ .ops = &clk_pixel_ops,
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+ .flags = CLK_SET_RATE_PARENT,
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},
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};
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@@ -754,41 +769,36 @@ static struct clk_rcg2 cpp_clk_src = {
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},
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};
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-static struct freq_tbl ftbl_mdss_byte0_clk[] = {
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- F(93750000, P_DSI0PLL, 8, 0, 0),
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- F(187500000, P_DSI0PLL, 4, 0, 0),
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- { }
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-};
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-
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-static struct freq_tbl ftbl_mdss_byte1_clk[] = {
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- F(93750000, P_DSI1PLL, 8, 0, 0),
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- F(187500000, P_DSI1PLL, 4, 0, 0),
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+static struct freq_tbl byte_freq_tbl[] = {
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+ { .src = P_DSI0PLL_BYTE },
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{ }
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};
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static struct clk_rcg2 byte0_clk_src = {
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.cmd_rcgr = 0x2120,
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.hid_width = 5,
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- .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
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- .freq_tbl = ftbl_mdss_byte0_clk,
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+ .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
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+ .freq_tbl = byte_freq_tbl,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "byte0_clk_src",
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- .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
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+ .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
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.num_parents = 6,
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- .ops = &clk_rcg2_ops,
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+ .ops = &clk_byte_ops,
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+ .flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_rcg2 byte1_clk_src = {
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.cmd_rcgr = 0x2140,
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.hid_width = 5,
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- .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
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- .freq_tbl = ftbl_mdss_byte1_clk,
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+ .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
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+ .freq_tbl = byte_freq_tbl,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "byte1_clk_src",
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- .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
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+ .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
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.num_parents = 6,
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- .ops = &clk_rcg2_ops,
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+ .ops = &clk_byte_ops,
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+ .flags = CLK_SET_RATE_PARENT,
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},
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};
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@@ -826,12 +836,12 @@ static struct clk_rcg2 edplink_clk_src =
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.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
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.num_parents = 6,
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.ops = &clk_rcg2_ops,
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+ .flags = CLK_SET_RATE_PARENT,
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},
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};
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-static struct freq_tbl ftbl_mdss_edppixel_clk[] = {
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- F(175000000, P_EDPVCO, 2, 0, 0),
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- F(350000000, P_EDPVCO, 11, 0, 0),
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+static struct freq_tbl edp_pixel_freq_tbl[] = {
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+ { .src = P_EDPVCO },
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{ }
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};
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@@ -840,12 +850,12 @@ static struct clk_rcg2 edppixel_clk_src
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = mmcc_xo_dsi_hdmi_edp_map,
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- .freq_tbl = ftbl_mdss_edppixel_clk,
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+ .freq_tbl = edp_pixel_freq_tbl,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "edppixel_clk_src",
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.parent_names = mmcc_xo_dsi_hdmi_edp,
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.num_parents = 6,
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- .ops = &clk_rcg2_ops,
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+ .ops = &clk_edp_pixel_ops,
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},
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};
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@@ -857,11 +867,11 @@ static struct freq_tbl ftbl_mdss_esc0_1_
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static struct clk_rcg2 esc0_clk_src = {
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.cmd_rcgr = 0x2160,
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.hid_width = 5,
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- .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
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+ .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
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.freq_tbl = ftbl_mdss_esc0_1_clk,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "esc0_clk_src",
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- .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
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+ .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
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.num_parents = 6,
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.ops = &clk_rcg2_ops,
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},
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@@ -870,26 +880,18 @@ static struct clk_rcg2 esc0_clk_src = {
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static struct clk_rcg2 esc1_clk_src = {
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.cmd_rcgr = 0x2180,
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.hid_width = 5,
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- .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
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+ .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
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.freq_tbl = ftbl_mdss_esc0_1_clk,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "esc1_clk_src",
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- .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
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+ .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
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.num_parents = 6,
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.ops = &clk_rcg2_ops,
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},
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};
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-static struct freq_tbl ftbl_mdss_extpclk_clk[] = {
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- F(25200000, P_HDMIPLL, 1, 0, 0),
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- F(27000000, P_HDMIPLL, 1, 0, 0),
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- F(27030000, P_HDMIPLL, 1, 0, 0),
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- F(65000000, P_HDMIPLL, 1, 0, 0),
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- F(74250000, P_HDMIPLL, 1, 0, 0),
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- F(108000000, P_HDMIPLL, 1, 0, 0),
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- F(148500000, P_HDMIPLL, 1, 0, 0),
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- F(268500000, P_HDMIPLL, 1, 0, 0),
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- F(297000000, P_HDMIPLL, 1, 0, 0),
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+static struct freq_tbl extpclk_freq_tbl[] = {
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+ { .src = P_HDMIPLL },
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{ }
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};
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@@ -897,12 +899,13 @@ static struct clk_rcg2 extpclk_clk_src =
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.cmd_rcgr = 0x2060,
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.hid_width = 5,
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.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
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- .freq_tbl = ftbl_mdss_extpclk_clk,
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+ .freq_tbl = extpclk_freq_tbl,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "extpclk_clk_src",
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.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
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.num_parents = 6,
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- .ops = &clk_rcg2_ops,
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+ .ops = &clk_byte_ops,
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+ .flags = CLK_SET_RATE_PARENT,
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},
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};
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