mirror of https://github.com/hak5/openwrt-owl.git
230 lines
6.0 KiB
Diff
230 lines
6.0 KiB
Diff
From c5f51197b13fd312324ac0486a46e530e163eade Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 14 Jul 2013 23:31:19 +0200
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Subject: [PATCH 18/33] USB: phy: add ralink SoC driver
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/usb/phy/Kconfig | 8 ++
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drivers/usb/phy/Makefile | 1 +
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drivers/usb/phy/ralink-phy.c | 191 ++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 200 insertions(+)
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create mode 100644 drivers/usb/phy/ralink-phy.c
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--- a/drivers/usb/phy/Kconfig
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+++ b/drivers/usb/phy/Kconfig
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@@ -210,4 +210,12 @@ config USB_ULPI_VIEWPORT
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Provides read/write operations to the ULPI phy register set for
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controllers with a viewport register (e.g. Chipidea/ARC controllers).
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+config RALINK_USBPHY
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+ bool "Ralink USB PHY controller Driver"
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+ depends on MIPS && RALINK
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+ select USB_OTG_UTILS
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+ help
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+ Enable this to support ralink USB phy controller for ralink
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+ SoCs.
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+
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endif # USB_PHY
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--- a/drivers/usb/phy/Makefile
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+++ b/drivers/usb/phy/Makefile
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@@ -31,3 +31,4 @@ obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-us
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obj-$(CONFIG_USB_RCAR_PHY) += phy-rcar-usb.o
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obj-$(CONFIG_USB_ULPI) += phy-ulpi.o
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obj-$(CONFIG_USB_ULPI_VIEWPORT) += phy-ulpi-viewport.o
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+obj-$(CONFIG_RALINK_USBPHY) += ralink-phy.o
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--- /dev/null
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+++ b/drivers/usb/phy/ralink-phy.c
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@@ -0,0 +1,191 @@
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+/*
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ *
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+ * based on: Renesas R-Car USB phy driver
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/delay.h>
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+#include <linux/io.h>
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+#include <linux/usb/otg.h>
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+#include <linux/of_platform.h>
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+#include <linux/platform_device.h>
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+#include <linux/spinlock.h>
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+#include <linux/module.h>
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+#include <linux/reset.h>
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+
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+#include <asm/mach-ralink/ralink_regs.h>
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+
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+#define RT_SYSC_REG_SYSCFG1 0x014
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+#define RT_SYSC_REG_CLKCFG1 0x030
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+#define RT_SYSC_REG_USB_PHY_CFG 0x05c
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+
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+#define RT_RSTCTRL_UDEV BIT(25)
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+#define RT_RSTCTRL_UHST BIT(22)
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+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
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+
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+#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
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+#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
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+#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
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+
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+#define USB_PHY_UTMI_8B60M BIT(1)
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+#define UDEV_WAKEUP BIT(0)
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+
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+static atomic_t usb_pwr_ref = ATOMIC_INIT(0);
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+static struct reset_control *rstdev;
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+static struct reset_control *rsthost;
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+static u32 phy_clk;
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+
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+static void usb_phy_enable(int state)
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+{
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+ if (state)
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+ rt_sysc_m32(0, phy_clk, RT_SYSC_REG_CLKCFG1);
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+ else
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+ rt_sysc_m32(phy_clk, 0, RT_SYSC_REG_CLKCFG1);
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+ mdelay(100);
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+}
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+
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+static int usb_power_on(struct usb_phy *phy)
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+{
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+ if (atomic_inc_return(&usb_pwr_ref) == 1) {
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+ u32 t;
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+
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+ usb_phy_enable(1);
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+
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+// reset_control_assert(rstdev);
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+// reset_control_assert(rsthost);
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+
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+ if (OTG_STATE_B_HOST) {
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+ rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
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+ reset_control_deassert(rsthost);
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+ } else {
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+ rt_sysc_m32(RT_SYSCFG1_USB0_HOST_MODE, 0, RT_SYSC_REG_SYSCFG1);
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+ reset_control_deassert(rstdev);
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+ }
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+ mdelay(100);
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+
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+ t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
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+ dev_info(phy->dev, "remote usb device wakeup %s\n",
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+ (t & UDEV_WAKEUP) ? ("enabbled") : ("disabled"));
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+ if (t & USB_PHY_UTMI_8B60M)
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+ dev_info(phy->dev, "UTMI 8bit 60MHz\n");
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+ else
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+ dev_info(phy->dev, "UTMI 16bit 30MHz\n");
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+ }
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+
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+ return 0;
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+}
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+
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+static void usb_power_off(struct usb_phy *phy)
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+{
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+ if (atomic_dec_return(&usb_pwr_ref) == 0) {
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+ usb_phy_enable(0);
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+ reset_control_assert(rstdev);
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+ reset_control_assert(rsthost);
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+ }
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+}
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+
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+static int usb_set_host(struct usb_otg *otg, struct usb_bus *host)
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+{
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+ otg->gadget = NULL;
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+ otg->host = host;
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+
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+ return 0;
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+}
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+
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+static int usb_set_peripheral(struct usb_otg *otg,
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+ struct usb_gadget *gadget)
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+{
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+ otg->host = NULL;
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+ otg->gadget = gadget;
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id ralink_usbphy_dt_match[] = {
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+ { .compatible = "ralink,rt3xxx-usbphy", .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN | RT_CLKCFG1_UPHY0_CLK_EN) },
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+ { .compatible = "ralink,mt7620a-usbphy", .data = (void *) MT7620_CLKCFG1_UPHY0_CLK_EN },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, ralink_usbphy_dt_match);
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+
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+static int usb_phy_probe(struct platform_device *pdev)
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+{
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+ const struct of_device_id *match;
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+ struct device *dev = &pdev->dev;
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+ struct usb_otg *otg;
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+ struct usb_phy *phy;
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+ int ret;
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+
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+ match = of_match_device(ralink_usbphy_dt_match, &pdev->dev);
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+ phy_clk = (int) match->data;
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+
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+ rsthost = devm_reset_control_get(&pdev->dev, "host");
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+ if (IS_ERR(rsthost))
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+ return PTR_ERR(rsthost);
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+
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+ rstdev = devm_reset_control_get(&pdev->dev, "device");
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+ if (IS_ERR(rstdev))
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+ return PTR_ERR(rstdev);
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+
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+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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+ if (!phy) {
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+ dev_err(&pdev->dev, "unable to allocate memory for USB PHY\n");
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+ return -ENOMEM;
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+ }
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+
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+ otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
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+ if (!otg) {
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+ dev_err(&pdev->dev, "unable to allocate memory for USB OTG\n");
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+ return -ENOMEM;
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+ }
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+
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+ phy->dev = dev;
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+ phy->label = dev_name(dev);
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+ phy->init = usb_power_on;
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+ phy->shutdown = usb_power_off;
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+ otg->set_host = usb_set_host;
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+ otg->set_peripheral = usb_set_peripheral;
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+ otg->phy = phy;
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+ phy->otg = otg;
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+ ret = usb_add_phy(phy, USB_PHY_TYPE_USB2);
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+
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+ if (ret < 0) {
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+ dev_err(dev, "usb phy addition error\n");
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+ return ret;
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+ }
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+
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+ platform_set_drvdata(pdev, phy);
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+
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+ dev_info(&pdev->dev, "loaded\n");
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+
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+ return ret;
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+}
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+
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+static int usb_phy_remove(struct platform_device *pdev)
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+{
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+ struct usb_phy *phy = platform_get_drvdata(pdev);
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+
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+ usb_remove_phy(phy);
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+
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+ return 0;
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+}
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+
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+static struct platform_driver usb_phy_driver = {
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+ .driver = {
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+ .owner = THIS_MODULE,
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+ .name = "rt3xxx-usbphy",
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+ .of_match_table = of_match_ptr(ralink_usbphy_dt_match),
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+ },
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+ .probe = usb_phy_probe,
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+ .remove = usb_phy_remove,
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+};
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+
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+module_platform_driver(usb_phy_driver);
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+
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+MODULE_LICENSE("GPL v2");
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+MODULE_DESCRIPTION("Ralink USB phy");
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+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
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