mirror of https://github.com/hak5/openwrt-owl.git
70 lines
2.5 KiB
Diff
70 lines
2.5 KiB
Diff
From 9eabaa2969af9aa157d50b7cfbb447f65db95f06 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 11 Aug 2011 12:25:55 +0200
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Subject: [PATCH 04/70] MIPS: lantiq: make irq.c support the FALC-ON
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There are minor differences in how irqs work on xway and falcon socs.
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Xway needs 2 quirks that we need to disable for falcon to also work with
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this code.
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* EBU irq does not need to send a special ack to the EBU
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* The EIU does not exist
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Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/lantiq/irq.c | 24 +++++++++++++-----------
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1 files changed, 13 insertions(+), 11 deletions(-)
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--- a/arch/mips/lantiq/irq.c
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+++ b/arch/mips/lantiq/irq.c
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@@ -195,7 +195,7 @@ static void ltq_hw_irqdispatch(int modul
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do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
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/* if this is a EBU irq, we need to ack it or get a deadlock */
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- if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0))
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+ if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
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ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
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LTQ_EBU_PCC_ISTAT);
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}
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@@ -259,17 +259,19 @@ void __init arch_init_irq(void)
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if (!ltq_icu_membase)
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panic("Failed to remap icu memory");
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- if (insert_resource(&iomem_resource, <q_eiu_resource) < 0)
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- panic("Failed to insert eiu memory");
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+ if (LTQ_EIU_BASE_ADDR) {
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+ if (insert_resource(&iomem_resource, <q_eiu_resource) < 0)
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+ panic("Failed to insert eiu memory\n");
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+
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+ if (request_mem_region(ltq_eiu_resource.start,
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+ resource_size(<q_eiu_resource), "eiu") < 0)
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+ panic("Failed to request eiu memory\n");
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- if (request_mem_region(ltq_eiu_resource.start,
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- resource_size(<q_eiu_resource), "eiu") < 0)
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- panic("Failed to request eiu memory");
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-
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- ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
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+ ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
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resource_size(<q_eiu_resource));
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- if (!ltq_eiu_membase)
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- panic("Failed to remap eiu memory");
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+ if (!ltq_eiu_membase)
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+ panic("Failed to remap eiu memory\n");
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+ }
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/* make sure all irqs are turned off by default */
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for (i = 0; i < 5; i++)
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@@ -295,8 +297,8 @@ void __init arch_init_irq(void)
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for (i = INT_NUM_IRQ0;
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i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
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- if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
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- (i == LTQ_EIU_IR2))
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+ if (((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
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+ (i == LTQ_EIU_IR2)) && LTQ_EIU_BASE_ADDR)
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irq_set_chip_and_handler(i, <q_eiu_type,
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handle_level_irq);
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/* EIU3-5 only exist on ar9 and vr9 */
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