mirror of https://github.com/hak5/openwrt-owl.git
104 lines
3.2 KiB
Diff
104 lines
3.2 KiB
Diff
--- a/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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@@ -138,6 +138,7 @@ static int cns3xxx_set_oneshot(struct cl
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/* period set, and timer enabled in 'next_event' hook */
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ctrl |= (1 << 2) | (1 << 9);
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+ writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
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writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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return 0;
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}
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@@ -148,7 +149,7 @@ static int cns3xxx_set_periodic(struct c
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int pclk = cns3xxx_cpu_clock() / 8;
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int reload;
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- reload = pclk * 20 / (3 * HZ) * 0x25000;
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+ reload = pclk * 1000000 / HZ;
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writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
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ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
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writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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@@ -175,7 +176,7 @@ static struct clock_event_device cns3xxx
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.set_state_oneshot = cns3xxx_set_oneshot,
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.tick_resume = cns3xxx_shutdown,
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.set_next_event = cns3xxx_timer_set_next_event,
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- .rating = 350,
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+ .rating = 300,
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.cpumask = cpu_all_mask,
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};
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@@ -220,6 +221,32 @@ static void __init cns3xxx_init_twd(void
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twd_local_timer_register(&cns3xx_twd_local_timer);
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}
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+static cycle_t cns3xxx_get_cycles(struct clocksource *cs)
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+{
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+ u64 val;
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+
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+ val = readl(cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
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+ val &= 0xffff;
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+
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+ return ((val << 32) | readl(cns3xxx_tmr1 + TIMER_FREERUN_OFFSET));
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+}
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+
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+static struct clocksource clocksource_cns3xxx = {
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+ .name = "freerun",
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+ .rating = 200,
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+ .read = cns3xxx_get_cycles,
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+ .mask = CLOCKSOURCE_MASK(48),
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+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
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+};
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+
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+static void __init cns3xxx_clocksource_init(void)
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+{
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+ /* Reset the FreeRunning counter */
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+ writel((1 << 16), cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
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+
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+ clocksource_register_khz(&clocksource_cns3xxx, 100);
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+}
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+
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/*
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* Set up the clock source and clock events devices
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*/
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@@ -237,13 +264,12 @@ static void __init __cns3xxx_timer_init(
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/* stop free running timer3 */
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writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
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- /* timer1 */
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- writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
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- writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
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-
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writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
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writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
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+ val = (cns3xxx_cpu_clock() >> 3) * 1000000 / HZ;
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+ writel(val, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
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+
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/* mask irq, non-mask timer1 overflow */
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irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
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irq_mask &= ~(1 << 2);
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@@ -255,23 +281,9 @@ static void __init __cns3xxx_timer_init(
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val |= (1 << 9);
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writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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- /* timer2 */
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- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
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- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
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-
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- /* mask irq */
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- irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
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- irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
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- writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
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-
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- /* down counter */
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- val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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- val |= (1 << 10);
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- writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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-
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- /* Make irqs happen for the system timer */
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setup_irq(timer_irq, &cns3xxx_timer_irq);
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+ cns3xxx_clocksource_init();
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cns3xxx_clockevents_init(timer_irq);
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cns3xxx_init_twd();
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}
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