mirror of https://github.com/hak5/openwrt-owl.git
377 lines
9.7 KiB
Diff
377 lines
9.7 KiB
Diff
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
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index 5b34ff29ea38..178b017be827 100644
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--- a/drivers/pwm/Kconfig
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+++ b/drivers/pwm/Kconfig
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@@ -217,6 +217,15 @@ config PWM_SPEAR
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To compile this driver as a module, choose M here: the module
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will be called pwm-spear.
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+config PWM_SUNXI
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+ tristate "Allwinner PWM support"
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+ depends on ARCH_SUNXI || COMPILE_TEST
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+ help
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+ Generic PWM framework driver for Allwinner SoCs.
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+
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+ To compile this driver as a module, choose M here: the module
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+ will be called pwm-sunxi.
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+
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config PWM_TEGRA
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tristate "NVIDIA Tegra PWM support"
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depends on ARCH_TEGRA
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diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
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index e57d2c38a794..39997ea2e276 100644
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--- a/drivers/pwm/Makefile
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+++ b/drivers/pwm/Makefile
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@@ -19,6 +19,7 @@ obj-$(CONFIG_PWM_PXA) += pwm-pxa.o
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obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
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obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
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obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
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+obj-$(CONFIG_PWM_SUNXI) += pwm-sunxi.o
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obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
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obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o
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obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o
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diff --git a/drivers/pwm/pwm-sunxi.c b/drivers/pwm/pwm-sunxi.c
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new file mode 100644
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index 000000000000..e7c3ca1d3c42
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--- /dev/null
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+++ b/drivers/pwm/pwm-sunxi.c
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@@ -0,0 +1,338 @@
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+/*
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+ * Driver for Allwinner Pulse Width Modulation Controller
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+ *
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+ * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
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+ *
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+ * Licensed under GPLv2.
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+ */
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+
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+#include <linux/bitops.h>
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+#include <linux/clk.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/of.h>
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+#include <linux/of_device.h>
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+#include <linux/platform_device.h>
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+#include <linux/pwm.h>
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+#include <linux/module.h>
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+#include <linux/mutex.h>
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+#include <linux/slab.h>
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+
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+#define PWM_CTRL_REG 0x0
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+
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+#define PWM_CH_PRD_BASE 0x4
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+#define PWM_CH_PRD_OFF 0x4
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+#define PWM_CH_PRD(x) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFF * (x))
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+
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+#define PWMCH_OFFSET 15
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+#define PWM_PRESCAL_MASK GENMASK(3, 0)
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+#define PWM_PRESCAL_OFF 0
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+#define PWM_EN BIT(4)
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+#define PWM_ACT_STATE BIT(5)
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+#define PWM_CLK_GATING BIT(6)
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+#define PWM_MODE BIT(7)
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+#define PWM_PULSE BIT(8)
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+#define PWM_BYPASS BIT(9)
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+
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+#define PWM_RDY_BASE 28
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+#define PWM_RDY_OFF 1
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+#define PWM_RDY(x) BIT(PWM_RDY_BASE + PWM_RDY_OFF * (x))
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+
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+#define PWM_PRD_ACT_MASK GENMASK(7, 0)
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+#define PWM_PRD(x) ((x - 1) << 16)
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+#define PWM_PRD_MASK GENMASK(7, 0)
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+
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+#define BIT_CH(bit, chan) (bit << (chan * PWMCH_OFFSET))
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+
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+u32 prescal_table[] = { 120, 180, 240, 360, 480, 0, 0, 0,
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+ 12000, 24000, 36000, 48000, 72000,
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+ 0, 0, 1 };
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+
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+struct sunxi_pwm_data {
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+ bool has_rdy;
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+};
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+
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+struct sunxi_pwm_chip {
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+ struct pwm_chip chip;
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+ struct clk *clk;
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+ void __iomem *base;
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+ struct mutex ctrl_lock;
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+ const struct sunxi_pwm_data *data;
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+};
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+
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+#define to_sunxi_pwm_chip(chip) container_of(chip, struct sunxi_pwm_chip, chip)
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+
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+static inline u32 sunxi_pwm_readl(struct sunxi_pwm_chip *chip,
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+ unsigned long offset)
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+{
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+ return readl(chip->base + offset);
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+}
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+
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+static inline void sunxi_pwm_writel(struct sunxi_pwm_chip *chip,
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+ unsigned long offset, unsigned long val)
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+{
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+ writel(val, chip->base + offset);
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+}
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+
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+static int sunxi_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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+ int duty_ns, int period_ns)
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+{
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+ struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip);
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+ u32 clk_rate, prd, dty;
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+ u64 div;
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+ u32 val, clk_gate;
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+ int i, ret;
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+
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+ clk_rate = clk_get_rate(sunxi_pwm->clk);
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+
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+ /* First, test without any divider */
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+ i = PWM_PRESCAL_MASK;
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+ div = clk_rate * period_ns;
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+ do_div(div, 1000000000);
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+ if (div > PWM_PRD_MASK) {
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+ /* Then go up from the first divider */
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+ for (i = 0; i < PWM_PRESCAL_MASK; i++) {
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+ if (!prescal_table[i])
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+ continue;
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+ div = clk_rate / prescal_table[i];
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+ div = div * period_ns;
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+ do_div(div, 1000000000);
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+ if (div <= PWM_PRD_MASK)
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+ break;
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+ }
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+ }
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+
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+ if (div > PWM_PRD_MASK) {
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+ dev_err(chip->dev, "prescaler exceeds the maximum value\n");
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+ return -EINVAL;
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+ }
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+
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+ prd = div;
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+ div *= duty_ns;
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+ do_div(div, period_ns);
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+ dty = div;
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+
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+ ret = clk_prepare_enable(sunxi_pwm->clk);
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+ if (ret) {
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+ dev_err(chip->dev, "failed to enable PWM clock\n");
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+ return ret;
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+ }
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+
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+ mutex_lock(&sunxi_pwm->ctrl_lock);
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+ val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
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+
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+ if (sunxi_pwm->data->has_rdy && (val & PWM_RDY(pwm->hwpwm))) {
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+ mutex_unlock(&sunxi_pwm->ctrl_lock);
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+ clk_disable_unprepare(sunxi_pwm->clk);
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+ return -EBUSY;
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+ }
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+
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+ clk_gate = val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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+ if (clk_gate) {
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+ val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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+ sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
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+ }
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+
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+ val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
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+ val &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
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+ val |= i;
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+ sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
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+
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+ sunxi_pwm_writel(sunxi_pwm, PWM_CH_PRD(pwm->hwpwm), dty | PWM_PRD(prd));
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+
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+ if (clk_gate) {
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+ val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
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+ val |= clk_gate;
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+ sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
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+ }
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+
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+ mutex_unlock(&sunxi_pwm->ctrl_lock);
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+ clk_disable_unprepare(sunxi_pwm->clk);
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+
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+ return 0;
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+}
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+
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+static int sunxi_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
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+ enum pwm_polarity polarity)
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+{
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+ struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip);
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+ u32 val;
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+ int ret;
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+
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+ ret = clk_prepare_enable(sunxi_pwm->clk);
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+ if (ret) {
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+ dev_err(chip->dev, "failed to enable PWM clock\n");
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+ return ret;
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+ }
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+
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+ mutex_lock(&sunxi_pwm->ctrl_lock);
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+ val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
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+
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+ if (polarity != PWM_POLARITY_NORMAL)
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+ val &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
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+ else
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+ val |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
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+
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+
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+ sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
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+
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+ mutex_unlock(&sunxi_pwm->ctrl_lock);
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+ clk_disable_unprepare(sunxi_pwm->clk);
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+
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+ return 0;
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+}
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+
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+static int sunxi_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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+{
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+ struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip);
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+ u32 val;
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+ int ret;
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+
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+ ret = clk_prepare_enable(sunxi_pwm->clk);
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+ if (ret) {
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+ dev_err(chip->dev, "failed to enable PWM clock\n");
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+ return ret;
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+ }
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+
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+ mutex_lock(&sunxi_pwm->ctrl_lock);
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+ val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
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+ val |= BIT_CH(PWM_EN, pwm->hwpwm);
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+ val |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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+ sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
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+ mutex_unlock(&sunxi_pwm->ctrl_lock);
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+
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+ return 0;
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+}
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+
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+static void sunxi_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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+{
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+ struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip);
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+ u32 val;
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+
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+ mutex_lock(&sunxi_pwm->ctrl_lock);
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+ val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
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+ val &= ~BIT_CH(PWM_EN, pwm->hwpwm);
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+ val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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+ sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
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+ mutex_unlock(&sunxi_pwm->ctrl_lock);
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+
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+ clk_disable_unprepare(sunxi_pwm->clk);
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+}
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+
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+static const struct pwm_ops sunxi_pwm_ops = {
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+ .config = sunxi_pwm_config,
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+ .set_polarity = sunxi_pwm_set_polarity,
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+ .enable = sunxi_pwm_enable,
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+ .disable = sunxi_pwm_disable,
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+ .owner = THIS_MODULE,
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+};
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+
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+static const struct sunxi_pwm_data sunxi_pwm_data_a10 = {
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+ .has_rdy = false,
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+};
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+
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+static const struct sunxi_pwm_data sunxi_pwm_data_a20 = {
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+ .has_rdy = true,
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+};
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+
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+static const struct of_device_id sunxi_pwm_dt_ids[] = {
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+ {
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+ .compatible = "allwinner,sun4i-a10-pwm",
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+ .data = &sunxi_pwm_data_a10,
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+ }, {
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+ .compatible = "allwinner,sun7i-a20-pwm",
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+ .data = &sunxi_pwm_data_a20,
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+ }, {
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+ /* sentinel */
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+ },
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+};
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+MODULE_DEVICE_TABLE(of, sunxi_pwm_dt_ids);
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+
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+static int sunxi_pwm_probe(struct platform_device *pdev)
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+{
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+ struct sunxi_pwm_chip *sunxi_pwm;
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+ struct resource *res;
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+ int ret;
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+
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+ const struct of_device_id *match;
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+
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+ match = of_match_device(sunxi_pwm_dt_ids, &pdev->dev);
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+ if (!match || !match->data)
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+ return -ENODEV;
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+
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+ sunxi_pwm = devm_kzalloc(&pdev->dev, sizeof(*sunxi_pwm), GFP_KERNEL);
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+ if (!sunxi_pwm)
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+ return -ENOMEM;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ sunxi_pwm->base = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(sunxi_pwm->base))
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+ return PTR_ERR(sunxi_pwm->base);
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+
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+ sunxi_pwm->clk = devm_clk_get(&pdev->dev, NULL);
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+ if (IS_ERR(sunxi_pwm->clk))
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+ return PTR_ERR(sunxi_pwm->clk);
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+
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+ sunxi_pwm->chip.dev = &pdev->dev;
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+ sunxi_pwm->chip.ops = &sunxi_pwm_ops;
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+
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+ sunxi_pwm->chip.base = -1;
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+ sunxi_pwm->chip.npwm = 2;
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+ sunxi_pwm->chip.can_sleep = true;
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+ sunxi_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
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+ sunxi_pwm->chip.of_pwm_n_cells = 3;
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+ sunxi_pwm->data = match->data;
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+
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+ mutex_init(&sunxi_pwm->ctrl_lock);
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+
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+ ret = clk_prepare_enable(sunxi_pwm->clk);
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+ if (ret) {
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+ dev_err(&pdev->dev, "failed to enable PWM clock\n");
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+ goto error;
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+ }
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+
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+ /* By default, the polarity is inversed, set it to normal */
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+ sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG,
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+ BIT_CH(PWM_ACT_STATE, 0) |
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+ BIT_CH(PWM_ACT_STATE, 1));
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+ clk_disable_unprepare(sunxi_pwm->clk);
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+
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+ ret = pwmchip_add(&sunxi_pwm->chip);
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+ if (ret < 0) {
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+ dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
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+ goto error;
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+ }
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+
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+ platform_set_drvdata(pdev, sunxi_pwm);
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+
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+ return ret;
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+
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+error:
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+ mutex_destroy(&sunxi_pwm->ctrl_lock);
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+ clk_disable_unprepare(sunxi_pwm->clk);
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+ return ret;
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+}
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+
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+static int sunxi_pwm_remove(struct platform_device *pdev)
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+{
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+ struct sunxi_pwm_chip *sunxi_pwm = platform_get_drvdata(pdev);
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+
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+ mutex_destroy(&sunxi_pwm->ctrl_lock);
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+
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+ return pwmchip_remove(&sunxi_pwm->chip);
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+}
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+
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+static struct platform_driver sunxi_pwm_driver = {
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+ .driver = {
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+ .name = "sunxi-pwm",
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+ .of_match_table = sunxi_pwm_dt_ids,
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+ },
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+ .probe = sunxi_pwm_probe,
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+ .remove = sunxi_pwm_remove,
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+};
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+module_platform_driver(sunxi_pwm_driver);
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+
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+MODULE_ALIAS("platform:sunxi-pwm");
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+MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
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+MODULE_DESCRIPTION("Allwinner PWM driver");
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+MODULE_LICENSE("GPL v2");
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