mirror of https://github.com/hak5/openwrt-owl.git
165 lines
3.3 KiB
Diff
165 lines
3.3 KiB
Diff
From 45e797ec7555c50775d9ac7fc7a17a544344aa3f Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 21 Mar 2013 17:47:07 +0100
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Subject: [PATCH 105/121] MIPS: extend RT3050 dtsi file
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Add some additional properties to the dtsi file for ethernet and wifi.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/dts/rt3050.dtsi | 96 ++++++++++++++++++++++++++++++++------
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1 file changed, 81 insertions(+), 15 deletions(-)
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diff --git a/arch/mips/ralink/dts/rt3050.dtsi b/arch/mips/ralink/dts/rt3050.dtsi
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index 069d066..5aede8d 100644
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--- a/arch/mips/ralink/dts/rt3050.dtsi
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+++ b/arch/mips/ralink/dts/rt3050.dtsi
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@@ -1,7 +1,7 @@
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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- compatible = "ralink,rt3050-soc", "ralink,rt3052-soc";
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+ compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
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cpus {
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cpu@0 {
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@@ -23,7 +23,7 @@
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palmbus@10000000 {
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compatible = "palmbus";
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reg = <0x10000000 0x200000>;
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- ranges = <0x0 0x10000000 0x1FFFFF>;
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+ ranges = <0x0 0x10000000 0x1FFFFF>;
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#address-cells = <1>;
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#size-cells = <1>;
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@@ -34,8 +34,18 @@
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};
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timer@100 {
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+ compatible = "ralink,rt3052-timer", "ralink,rt2880-timer";
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+ reg = <0x100 0x20>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <1>;
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+
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+ status = "disabled";
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+ };
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+
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+ watchdog@120 {
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compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
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- reg = <0x100 0x100>;
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+ reg = <0x120 0x10>;
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};
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intc: intc@200 {
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@@ -61,10 +71,12 @@
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gpio-controller;
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#gpio-cells = <2>;
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- ralink,ngpio = <24>;
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- ralink,regs = [ 00 04 08 0c
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- 20 24 28 2c
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- 30 34 ];
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+ ralink,num-gpios = <24>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 20 24 28 2c
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+ 30 34 ];
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+
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+ status = "disabled";
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};
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gpio1: gpio@638 {
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@@ -74,10 +86,12 @@
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gpio-controller;
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#gpio-cells = <2>;
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- ralink,ngpio = <16>;
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- ralink,regs = [ 00 04 08 0c
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- 10 14 18 1c
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- 20 24 ];
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+ ralink,num-gpios = <16>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+
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+ status = "disabled";
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};
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gpio2: gpio@660 {
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@@ -87,10 +101,21 @@
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gpio-controller;
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#gpio-cells = <2>;
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- ralink,ngpio = <12>;
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- ralink,regs = [ 00 04 08 0c
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- 10 14 18 1c
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- 20 24 ];
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+ ralink,num-gpios = <12>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+
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+ status = "disabled";
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+ };
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+
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+ spi@b00 {
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+ compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
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+ reg = <0xb00 0x100>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ status = "disabled";
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};
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uartlite@c00 {
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@@ -102,5 +127,46 @@
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reg-shift = <2>;
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};
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+
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+ };
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+
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+ ethernet@10100000 {
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+ compatible = "ralink,rt3050-eth";
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+ reg = <0x10100000 10000>;
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+
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+ interrupt-parent = <&cpuintc>;
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+ interrupts = <5>;
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+
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+ status = "disabled";
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+ };
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+
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+ esw@10110000 {
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+ compatible = "ralink,rt3050-esw";
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+ reg = <0x10110000 8000>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <17>;
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+
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+ status = "disabled";
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+ };
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+
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+ wmac@10180000 {
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+ compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac";
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+ reg = <0x10180000 40000>;
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+
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+ interrupt-parent = <&cpuintc>;
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+ interrupts = <6>;
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+
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+ status = "disabled";
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+ };
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+
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+ otg@101c0000 {
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+ compatible = "ralink,rt3050-otg";
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+ reg = <0x101c0000 40000>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <18>;
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+
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+ status = "disabled";
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};
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};
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--
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1.7.10.4
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