mirror of https://github.com/hak5/openwrt-owl.git
560 lines
14 KiB
Diff
560 lines
14 KiB
Diff
From 7288414298b34dcda1216fee1fe38d05ea0027a2 Mon Sep 17 00:00:00 2001
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From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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Date: Mon, 17 Dec 2012 23:32:39 +0100
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Subject: net: add driver for Lantiq XWAY ARX100 switch
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Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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diff --git a/arch/mips/include/asm/arch-arx100/config.h b/arch/mips/include/asm/arch-arx100/config.h
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index 1a6c9bc..8f955e8 100644
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--- a/arch/mips/include/asm/arch-arx100/config.h
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+++ b/arch/mips/include/asm/arch-arx100/config.h
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@@ -10,17 +10,21 @@
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* and drivers for this SoC:
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*
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* CONFIG_LTQ_SUPPORT_UART
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- * - support the Danube ASC/UART interface and console
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+ * - support the ARX100 ASC/UART interface and console
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*
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* CONFIG_LTQ_SUPPORT_NOR_FLASH
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* - support a parallel NOR flash via the CFI interface in flash bank 0
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*
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* CONFIG_LTQ_SUPPORT_ETHERNET
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- * - support the Danube ETOP and MAC interface
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+ * - support the ARX100 ETOP and MAC interface
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*
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* CONFIG_LTQ_SUPPORT_SPI_FLASH
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- * - support the Danube SPI interface and serial flash drivers
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+ * - support the ARX100 SPI interface and serial flash drivers
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* - specific SPI flash drivers must be configured separately
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+ *
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+ * CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH
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+ * - build a preloader that runs in the internal SRAM and loads
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+ * the U-Boot from SPI flash into RAM
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*/
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#ifndef __ARX100_CONFIG_H__
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diff --git a/arch/mips/include/asm/arch-arx100/switch.h b/arch/mips/include/asm/arch-arx100/switch.h
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new file mode 100644
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index 0000000..301056c
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--- /dev/null
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+++ b/arch/mips/include/asm/arch-arx100/switch.h
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@@ -0,0 +1,86 @@
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+/*
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+ * Copyright (C) 2012-2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#ifndef __ARX100_SWITCH_H__
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+#define __ARX100_SWITCH_H__
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+
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+struct ar9_switch_regs {
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+ __be32 ps; /* Port status*/
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+ __be32 p0_ctl; /* Port 0 control */
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+ __be32 p1_ctl; /* Port 1 control */
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+ __be32 p2_ctl; /* Port 2 control */
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+ __be32 p0_vlan; /* Port 0 VLAN control */
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+ __be32 p1_vlan; /* Port 1 VLAN control */
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+ __be32 p2_vlan; /* Port 2 VLAN control */
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+ __be32 p0_inctl; /* Port 0 ingress control */
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+ __be32 p1_inctl; /* Port 1 ingress control */
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+ __be32 p2_inctl; /* Port 2 ingress control */
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+ u32 rsvd0[16];
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+ __be32 sw_gctl0; /* Switch global control 0 */
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+ __be32 sw_gctl1; /* Switch global control 1 */
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+ __be32 arp; /* ARP/RARP */
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+ __be32 strm_ctl; /* Storm control */
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+ __be32 rgmii_ctl; /* RGMII/GMII port control */
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+ u32 rsvd1[4];
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+ __be32 pmac_hd_ctl; /* PMAC header control */
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+ u32 rsvd2[15];
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+ __be32 mdio_ctrl; /* MDIO indirect access control */
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+ __be32 mdio_data; /* MDIO indirect read data */
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+};
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+
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+#define BUILD_CHECK_AR9_REG(name, offset) \
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+ BUILD_BUG_ON(offsetof(struct ar9_switch_regs, name) != (offset))
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+
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+static inline void build_check_ar9_registers(void)
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+{
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+ BUILD_CHECK_AR9_REG(sw_gctl0, 0x68);
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+ BUILD_CHECK_AR9_REG(rgmii_ctl, 0x78);
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+ BUILD_CHECK_AR9_REG(pmac_hd_ctl, 0x8c);
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+ BUILD_CHECK_AR9_REG(mdio_ctrl, 0xcc);
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+ BUILD_CHECK_AR9_REG(mdio_data, 0xd0);
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+}
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+
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+#define P0_CTL_FLP (1 << 18)
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+#define P0_CTL_FLD (1 << 17)
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+
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+#define SW_GCTL0_SE (1 << 31)
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+
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+#define RGMII_CTL_P1_SHIFT 10
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+#define RGMII_CTL_P1_MASK (0x3FF << RGMII_CTL_P1_SHIFT)
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+#define RGMII_CTL_P0_MASK 0x3FF
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+#define RGMII_CTL_P0IS_SHIFT 8
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+#define RGMII_CTL_P0IS_RGMII (0x0 << RGMII_CTL_P0IS_SHIFT)
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+#define RGMII_CTL_P0IS_MII (0x1 << RGMII_CTL_P0IS_SHIFT)
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+#define RGMII_CTL_P0IS_REVMII (0x2 << RGMII_CTL_P0IS_SHIFT)
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+#define RGMII_CTL_P0IS_RMII (0x3 << RGMII_CTL_P0IS_SHIFT)
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+#define RGMII_CTL_P0RDLY_SHIFT 6
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+#define RGMII_CTL_P0RDLY_0_0 (0x0 << RGMII_CTL_P0RDLY_SHIFT)
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+#define RGMII_CTL_P0RDLY_1_5 (0x1 << RGMII_CTL_P0RDLY_SHIFT)
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+#define RGMII_CTL_P0RDLY_1_75 (0x2 << RGMII_CTL_P0RDLY_SHIFT)
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+#define RGMII_CTL_P0RDLY_2_0 (0x3 << RGMII_CTL_P0RDLY_SHIFT)
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+#define RGMII_CTL_P0TDLY_SHIFT 4
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+#define RGMII_CTL_P0TDLY_0_0 (0x0 << RGMII_CTL_P0TDLY_SHIFT)
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+#define RGMII_CTL_P0TDLY_1_5 (0x1 << RGMII_CTL_P0TDLY_SHIFT)
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+#define RGMII_CTL_P0TDLY_1_75 (0x2 << RGMII_CTL_P0TDLY_SHIFT)
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+#define RGMII_CTL_P0TDLY_2_0 (0x3 << RGMII_CTL_P0TDLY_SHIFT)
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+#define RGMII_CTL_P0SPD_SHIFT 2
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+#define RGMII_CTL_P0SPD_10 (0x0 << RGMII_CTL_P0SPD_SHIFT)
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+#define RGMII_CTL_P0SPD_100 (0x1 << RGMII_CTL_P0SPD_SHIFT)
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+#define RGMII_CTL_P0SPD_1000 (0x2 << RGMII_CTL_P0SPD_SHIFT)
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+#define RGMII_CTL_P0DUP_FULL (1 << 1)
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+#define RGMII_CTL_P0FCE_EN (1 << 0)
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+
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+#define PMAC_HD_CTL_AC (1 << 18)
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+
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+#define MDIO_CTRL_WD_SHIFT 16
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+#define MDIO_CTRL_MBUSY (1 << 15)
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+#define MDIO_CTRL_OP_READ (1 << 11)
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+#define MDIO_CTRL_OP_WRITE (1 << 10)
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+#define MDIO_CTRL_PHYAD_SHIFT 5
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+#define MDIO_CTRL_PHYAD_MASK (0x1f << MDIO_CTRL_PHYAD_SHIFT)
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+#define MDIO_CTRL_REGAD_MASK 0x1f
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+
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+#endif /* __ARX100_SWITCH_H__ */
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diff --git a/drivers/net/Makefile b/drivers/net/Makefile
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index bbc2c92..926b8c2 100644
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--- a/drivers/net/Makefile
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+++ b/drivers/net/Makefile
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@@ -38,6 +38,7 @@ COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
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COBJS-$(CONFIG_KS8851_MLL) += ks8851_mll.o
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COBJS-$(CONFIG_LAN91C96) += lan91c96.o
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COBJS-$(CONFIG_LANTIQ_DANUBE_ETOP) += lantiq_danube_etop.o
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+COBJS-$(CONFIG_LANTIQ_ARX100_SWITCH) += lantiq_arx100_switch.o
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COBJS-$(CONFIG_LANTIQ_VRX200_SWITCH) += lantiq_vrx200_switch.o
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COBJS-$(CONFIG_MACB) += macb.o
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COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
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diff --git a/drivers/net/lantiq_arx100_switch.c b/drivers/net/lantiq_arx100_switch.c
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new file mode 100644
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index 0000000..cc65249
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--- /dev/null
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+++ b/drivers/net/lantiq_arx100_switch.c
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@@ -0,0 +1,410 @@
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+/*
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+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+#define DEBUG
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+#include <common.h>
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+#include <malloc.h>
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+#include <netdev.h>
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+#include <miiphy.h>
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+#include <switch.h>
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+#include <linux/compiler.h>
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+#include <asm/gpio.h>
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+#include <asm/processor.h>
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+#include <asm/lantiq/io.h>
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+#include <asm/lantiq/eth.h>
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+#include <asm/lantiq/pm.h>
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+#include <asm/lantiq/reset.h>
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+#include <asm/lantiq/dma.h>
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+#include <asm/arch/soc.h>
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+#include <asm/arch/switch.h>
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+
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+#define LTQ_ETH_RX_BUFFER_CNT PKTBUFSRX
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+#define LTQ_ETH_TX_BUFFER_CNT 8
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+#define LTQ_ETH_RX_DATA_SIZE PKTSIZE_ALIGN
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+#define LTQ_ETH_IP_ALIGN 2
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+
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+#define LTQ_MDIO_DRV_NAME "ltq-mdio"
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+#define LTQ_ETH_DRV_NAME "ltq-eth"
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+
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+#define LTQ_ETHSW_MAX_GMAC 2
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+#define LTQ_ETHSW_PMAC 2
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+
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+struct ltq_eth_priv {
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+ struct ltq_dma_device dma_dev;
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+ struct mii_dev *bus;
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+ struct eth_device *dev;
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+ struct phy_device *phymap[LTQ_ETHSW_MAX_GMAC];
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+ int rx_num;
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+ int tx_num;
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+};
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+
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+static struct ar9_switch_regs *switch_regs =
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+ (struct ar9_switch_regs *) CKSEG1ADDR(LTQ_SWITCH_BASE);
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+
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+static int ltq_mdio_is_busy(void)
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+{
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+ u32 mdio_ctrl = ltq_readl(&switch_regs->mdio_ctrl);
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+
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+ return mdio_ctrl & MDIO_CTRL_MBUSY;
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+}
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+
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+static void ltq_mdio_poll(void)
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+{
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+ while (ltq_mdio_is_busy())
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+ cpu_relax();
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+
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+ __udelay(1000);
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+}
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+
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+static int ltq_mdio_read(struct mii_dev *bus, int phyad, int devad,
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+ int regad)
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+{
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+ u32 mdio_ctrl;
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+ int retval;
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+
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+ mdio_ctrl = MDIO_CTRL_MBUSY | MDIO_CTRL_OP_READ |
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+ ((phyad << MDIO_CTRL_PHYAD_SHIFT) & MDIO_CTRL_PHYAD_MASK) |
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+ (regad & MDIO_CTRL_REGAD_MASK);
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+
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+ ltq_mdio_poll();
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+ ltq_writel(&switch_regs->mdio_ctrl, mdio_ctrl);
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+ ltq_mdio_poll();
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+ retval = ltq_readl(&switch_regs->mdio_data);
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+ ltq_writel(&switch_regs->mdio_data, 0xFFFF);
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+
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+ debug("%s: phyad %02x, regad %02x, val %02x\n", __func__, phyad, regad, retval);
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+
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+ return retval;
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+}
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+
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+static int ltq_mdio_write(struct mii_dev *bus, int phyad, int devad,
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+ int regad, u16 val)
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+{
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+ u32 mdio_ctrl;
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+
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+ debug("%s: phyad %02x, regad %02x, val %02x\n", __func__, phyad, regad, val);
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+
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+ mdio_ctrl = (val << MDIO_CTRL_WD_SHIFT) | MDIO_CTRL_MBUSY |
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+ MDIO_CTRL_OP_WRITE |
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+ ((phyad << MDIO_CTRL_PHYAD_SHIFT) & MDIO_CTRL_PHYAD_MASK) |
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+ (regad & MDIO_CTRL_REGAD_MASK);
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+
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+ ltq_mdio_poll();
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+ ltq_writel(&switch_regs->mdio_ctrl, mdio_ctrl);
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+
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+ return 0;
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+}
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+
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+static void ltq_eth_gmac_update(struct phy_device *phydev, int num)
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+{
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+}
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+
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+static inline u8 *ltq_eth_rx_packet_align(int rx_num)
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+{
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+ u8 *packet = (u8 *) NetRxPackets[rx_num];
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+
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+ /*
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+ * IP header needs
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+ */
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+ return packet + LTQ_ETH_IP_ALIGN;
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+}
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+
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+static int ltq_eth_init(struct eth_device *dev, bd_t *bis)
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+{
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+ struct ltq_eth_priv *priv = dev->priv;
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+ struct ltq_dma_device *dma_dev = &priv->dma_dev;
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+ struct phy_device *phydev;
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+ int i;
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+
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+ for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) {
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+ phydev = priv->phymap[i];
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+ if (!phydev)
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+ continue;
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+
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+ phy_startup(phydev);
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+ ltq_eth_gmac_update(phydev, i);
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+ }
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+
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+ for (i = 0; i < LTQ_ETH_RX_BUFFER_CNT; i++)
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+ ltq_dma_rx_map(dma_dev, i, ltq_eth_rx_packet_align(i),
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+ LTQ_ETH_RX_DATA_SIZE);
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+
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+ ltq_dma_enable(dma_dev);
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+
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+ priv->rx_num = 0;
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+ priv->tx_num = 0;
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+
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+ return 0;
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+}
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+
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+static void ltq_eth_halt(struct eth_device *dev)
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+{
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+ struct ltq_eth_priv *priv = dev->priv;
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+ struct ltq_dma_device *dma_dev = &priv->dma_dev;
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+ struct phy_device *phydev;
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+ int i;
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+
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+ ltq_dma_reset(dma_dev);
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+
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+ for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) {
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+ phydev = priv->phymap[i];
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+ if (!phydev)
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+ continue;
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+
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+ phy_shutdown(phydev);
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+ phydev->link = 0;
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+ ltq_eth_gmac_update(phydev, i);
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+ }
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+}
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+
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+static int ltq_eth_send(struct eth_device *dev, void *packet, int length)
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+{
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+ struct ltq_eth_priv *priv = dev->priv;
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+ struct ltq_dma_device *dma_dev = &priv->dma_dev;
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+ int err;
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+
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+ err = ltq_dma_tx_map(dma_dev, priv->tx_num, packet, length, 10);
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+ if (err) {
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+ puts("NET: timeout on waiting for TX descriptor\n");
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+ return -1;
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+ }
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+
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+ priv->tx_num = (priv->tx_num + 1) % LTQ_ETH_TX_BUFFER_CNT;
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+
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+ return err;
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+}
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+
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+static int ltq_eth_recv(struct eth_device *dev)
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+{
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+ struct ltq_eth_priv *priv = dev->priv;
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+ struct ltq_dma_device *dma_dev = &priv->dma_dev;
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+ u8 *packet;
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+ int len;
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+
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+ if (!ltq_dma_rx_poll(dma_dev, priv->rx_num))
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+ return 0;
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+
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+#if 0
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+ printf("%s: rx_num %d\n", __func__, priv->rx_num);
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+#endif
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+
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+ len = ltq_dma_rx_length(dma_dev, priv->rx_num);
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+ packet = ltq_eth_rx_packet_align(priv->rx_num);
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+
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+#if 0
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+ printf("%s: received: packet %p, len %u, rx_num %d\n",
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+ __func__, packet, len, priv->rx_num);
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+#endif
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+
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+ if (len)
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+ NetReceive(packet, len);
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+
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+ ltq_dma_rx_map(dma_dev, priv->rx_num, packet,
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+ LTQ_ETH_RX_DATA_SIZE);
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+
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+ priv->rx_num = (priv->rx_num + 1) % LTQ_ETH_RX_BUFFER_CNT;
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+
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+ return 0;
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+}
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+
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+static void ltq_eth_pmac_init(void)
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+{
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+ /* Add CRC to packets from DMA to PMAC */
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+ ltq_setbits(&switch_regs->pmac_hd_ctl, PMAC_HD_CTL_AC);
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+
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+ /* Force link up */
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+ ltq_setbits(&switch_regs->p2_ctl, P0_CTL_FLP);
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+}
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+
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+static void ltq_eth_hw_init(const struct ltq_eth_port_config *port)
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+{
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+ /* Power up ethernet subsystems */
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+ ltq_pm_enable(LTQ_PM_ETH);
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+
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+ /* Enable switch core */
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+ ltq_setbits(&switch_regs->sw_gctl0, SW_GCTL0_SE);
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+
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+ /* MII/MDIO */
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+ gpio_set_altfunc(42, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
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+ /* MII/MDC */
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+ gpio_set_altfunc(43, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
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+
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+ ltq_eth_pmac_init();
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+}
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+
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+static void ltq_eth_port_config(struct ltq_eth_priv *priv,
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+ const struct ltq_eth_port_config *port)
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+{
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+ struct phy_device *phydev;
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+ struct switch_device *sw;
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+ u32 rgmii_ctl;
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+ unsigned int port_ctl, port_xmii = 0;
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+
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+ if (port->num > 1)
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+ return;
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+
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+ rgmii_ctl = ltq_readl(&switch_regs->rgmii_ctl);
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+
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+ if (port->num == 1)
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+ port_ctl = ltq_readl(&switch_regs->p1_ctl);
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+ else
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+ port_ctl = ltq_readl(&switch_regs->p0_ctl);
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+
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+ switch (port->phy_if) {
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+ case PHY_INTERFACE_MODE_RGMII:
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+ port_xmii = RGMII_CTL_P0IS_RGMII;
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+
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+ switch (port->rgmii_tx_delay) {
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+ case 1:
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+ port_xmii |= RGMII_CTL_P0TDLY_1_5;
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+ break;
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+ case 2:
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+ port_xmii |= RGMII_CTL_P0TDLY_1_75;
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+ break;
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|
+ case 3:
|
|
+ port_xmii |= RGMII_CTL_P0TDLY_2_0;
|
|
+ break;
|
|
+ default:
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ switch (port->rgmii_rx_delay) {
|
|
+ case 1:
|
|
+ port_xmii |= RGMII_CTL_P0RDLY_1_5;
|
|
+ break;
|
|
+ case 2:
|
|
+ port_xmii |= RGMII_CTL_P0RDLY_1_75;
|
|
+ break;
|
|
+ case 3:
|
|
+ port_xmii |= RGMII_CTL_P0RDLY_2_0;
|
|
+ break;
|
|
+ default:
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ if (!(port->flags & LTQ_ETH_PORT_PHY)) {
|
|
+ port_xmii |= (RGMII_CTL_P0SPD_1000 |
|
|
+ RGMII_CTL_P0DUP_FULL);
|
|
+ port_ctl |= P0_CTL_FLP;
|
|
+ }
|
|
+
|
|
+ break;
|
|
+ case PHY_INTERFACE_MODE_MII:
|
|
+ port_xmii = RGMII_CTL_P0IS_MII;
|
|
+
|
|
+ if (!(port->flags & LTQ_ETH_PORT_PHY)) {
|
|
+ port_xmii |= (RGMII_CTL_P0SPD_100 |
|
|
+ RGMII_CTL_P0DUP_FULL);
|
|
+ port_ctl |= P0_CTL_FLP;
|
|
+ }
|
|
+
|
|
+ break;
|
|
+ default:
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ if (port->num == 1) {
|
|
+ ltq_writel(&switch_regs->p1_ctl, port_ctl);
|
|
+
|
|
+ rgmii_ctl &= ~RGMII_CTL_P1_MASK;
|
|
+ rgmii_ctl |= (port_xmii << RGMII_CTL_P1_SHIFT);
|
|
+ } else {
|
|
+ ltq_writel(&switch_regs->p0_ctl, port_ctl);
|
|
+
|
|
+ rgmii_ctl &= ~RGMII_CTL_P0_MASK;
|
|
+ rgmii_ctl |= port_xmii;
|
|
+ }
|
|
+
|
|
+ ltq_writel(&switch_regs->rgmii_ctl, rgmii_ctl);
|
|
+
|
|
+ /* Connect to external switch */
|
|
+ if (port->flags & LTQ_ETH_PORT_SWITCH) {
|
|
+ sw = switch_connect(priv->bus);
|
|
+ if (sw)
|
|
+ switch_setup(sw);
|
|
+ }
|
|
+
|
|
+ /* Connect to internal/external PHYs */
|
|
+ if (port->flags & LTQ_ETH_PORT_PHY) {
|
|
+ phydev = phy_connect(priv->bus, port->phy_addr, priv->dev,
|
|
+ port->phy_if);
|
|
+ if (phydev)
|
|
+ phy_config(phydev);
|
|
+
|
|
+ priv->phymap[port->num] = phydev;
|
|
+ }
|
|
+}
|
|
+
|
|
+int ltq_eth_initialize(const struct ltq_eth_board_config *board_config)
|
|
+{
|
|
+ struct eth_device *dev;
|
|
+ struct mii_dev *bus;
|
|
+ struct ltq_eth_priv *priv;
|
|
+ struct ltq_dma_device *dma_dev;
|
|
+ const struct ltq_eth_port_config *port = &board_config->ports[0];
|
|
+ int i, ret;
|
|
+
|
|
+ build_check_ar9_registers();
|
|
+
|
|
+ ltq_dma_init();
|
|
+ ltq_eth_hw_init(port);
|
|
+
|
|
+ dev = calloc(1, sizeof(*dev));
|
|
+ if (!dev)
|
|
+ return -1;
|
|
+
|
|
+ priv = calloc(1, sizeof(*priv));
|
|
+ if (!priv)
|
|
+ return -1;
|
|
+
|
|
+ bus = mdio_alloc();
|
|
+ if (!bus)
|
|
+ return -1;
|
|
+
|
|
+ sprintf(dev->name, LTQ_ETH_DRV_NAME);
|
|
+ dev->priv = priv;
|
|
+ dev->init = ltq_eth_init;
|
|
+ dev->halt = ltq_eth_halt;
|
|
+ dev->recv = ltq_eth_recv;
|
|
+ dev->send = ltq_eth_send;
|
|
+
|
|
+ sprintf(bus->name, LTQ_MDIO_DRV_NAME);
|
|
+ bus->read = ltq_mdio_read;
|
|
+ bus->write = ltq_mdio_write;
|
|
+ bus->priv = priv;
|
|
+
|
|
+ dma_dev = &priv->dma_dev;
|
|
+ dma_dev->port = 0;
|
|
+ dma_dev->rx_chan.chan_no = 0;
|
|
+ dma_dev->rx_chan.class = 0;
|
|
+ dma_dev->rx_chan.num_desc = LTQ_ETH_RX_BUFFER_CNT;
|
|
+ dma_dev->rx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;
|
|
+ dma_dev->rx_burst_len = LTQ_DMA_BURST_2WORDS;
|
|
+ dma_dev->tx_chan.chan_no = 1;
|
|
+ dma_dev->tx_chan.class = 0;
|
|
+ dma_dev->tx_chan.num_desc = LTQ_ETH_TX_BUFFER_CNT;
|
|
+ dma_dev->tx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;
|
|
+ dma_dev->tx_burst_len = LTQ_DMA_BURST_2WORDS;
|
|
+
|
|
+ priv->bus = bus;
|
|
+ priv->dev = dev;
|
|
+
|
|
+ ret = ltq_dma_register(dma_dev);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ ret = mdio_register(bus);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ ret = eth_register(dev);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ for (i = 0; i < board_config->num_ports; i++)
|
|
+ ltq_eth_port_config(priv, &board_config->ports[i]);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
--
|
|
1.8.3.2
|
|
|