mirror of https://github.com/hak5/openwrt-owl.git
553 lines
15 KiB
Diff
553 lines
15 KiB
Diff
From 3ce895cbe3469bfcaa84674ec4f1b2d60e8b370b Mon Sep 17 00:00:00 2001
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From: Mingkai Hu <Mingkai.Hu@freescale.com>
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Date: Mon, 21 Jul 2014 14:48:42 +0800
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Subject: [PATCH 01/70] arm64/ls1043a: add DTS for Freescale LS1043A SoC
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LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks
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similar to LS1021a which complies to Chassis 2.1 spec.
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Following levels of DTSI/DTS files have been created for the
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LS1043A SoC family:
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- fsl-ls1043a.dtsi:
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DTS-Include file for FSL LS1043A SoC.
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Signed-off-by: Li Yang <leoli@freescale.com>
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Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
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Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
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Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com>
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Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 525 ++++++++++++++++++++++++
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1 file changed, 525 insertions(+)
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
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@@ -0,0 +1,525 @@
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+/*
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+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
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+ *
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+ * Copyright 2014-2015, Freescale Semiconductor
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+ *
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+ * Mingkai Hu <Mingkai.hu@freescale.com>
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+ *
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+ * This file is dual-licensed: you can use it either under the terms
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+ * of the GPLv2 or the X11 license, at your option. Note that this dual
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+ * licensing only applies to this file, and not this project as a
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+ * whole.
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+ *
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+ * a) This library is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of the
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+ * License, or (at your option) any later version.
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+ *
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+ * This library is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Or, alternatively,
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+ *
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+ * b) Permission is hereby granted, free of charge, to any person
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+ * obtaining a copy of this software and associated documentation
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+ * files (the "Software"), to deal in the Software without
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+ * restriction, including without limitation the rights to use,
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+ * copy, modify, merge, publish, distribute, sublicense, and/or
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+ * sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following
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+ * conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be
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+ * included in all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+
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+/ {
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+ compatible = "fsl,ls1043a";
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+ interrupt-parent = <&gic>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ cpus {
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+ #address-cells = <2>;
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+ #size-cells = <0>;
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+
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+ /*
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+ * We expect the enable-method for cpu's to be "psci", but this
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+ * is dependent on the SoC FW, which will fill this in.
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+ *
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+ * Currently supported enable-method is psci v0.2
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+ */
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+ cpu0: cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x0 0x0>;
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+ clocks = <&clockgen 1 0>;
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+ };
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+
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+ cpu1: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x0 0x1>;
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+ clocks = <&clockgen 1 0>;
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+ };
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+
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+ cpu2: cpu@2 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x0 0x2>;
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+ clocks = <&clockgen 1 0>;
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+ };
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+
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+ cpu3: cpu@3 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x0 0x3>;
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+ clocks = <&clockgen 1 0>;
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+ };
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+ };
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+
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+ memory@80000000 {
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+ device_type = "memory";
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+ reg = <0x0 0x80000000 0 0x80000000>;
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+ /* DRAM space 1, size: 2GiB DRAM */
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+ };
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+
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+ sysclk: sysclk {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <100000000>;
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+ clock-output-names = "sysclk";
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+ };
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+
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+ timer {
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+ compatible = "arm,armv8-timer";
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+ interrupts = <1 13 0x1>, /* Physical Secure PPI */
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+ <1 14 0x1>, /* Physical Non-Secure PPI */
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+ <1 11 0x1>, /* Virtual PPI */
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+ <1 10 0x1>; /* Hypervisor PPI */
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+ };
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+
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+ pmu {
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+ compatible = "arm,armv8-pmuv3";
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+ interrupts = <0 106 0x4>,
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+ <0 107 0x4>,
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+ <0 95 0x4>,
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+ <0 97 0x4>;
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+ interrupt-affinity = <&cpu0>,
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+ <&cpu1>,
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+ <&cpu2>,
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+ <&cpu3>;
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+ };
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+
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+ gic: interrupt-controller@1400000 {
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+ compatible = "arm,gic-400";
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+ #interrupt-cells = <3>;
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+ interrupt-controller;
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+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
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+ <0x0 0x1402000 0 0x2000>, /* GICC */
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+ <0x0 0x1404000 0 0x2000>, /* GICH */
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+ <0x0 0x1406000 0 0x2000>; /* GICV */
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+ interrupts = <1 9 0xf08>;
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+ };
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+
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+ soc {
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+ compatible = "simple-bus";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ clockgen: clocking@1ee1000 {
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+ compatible = "fsl,ls1043a-clockgen";
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+ reg = <0x0 0x1ee1000 0x0 0x1000>;
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+ #clock-cells = <2>;
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+ clocks = <&sysclk>;
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+ };
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+
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+ scfg: scfg@1570000 {
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+ compatible = "fsl,ls1043a-scfg", "syscon";
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+ reg = <0x0 0x1570000 0x0 0x10000>;
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+ big-endian;
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+ };
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+
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+ dcfg: dcfg@1ee0000 {
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+ compatible = "fsl,ls1043a-dcfg", "syscon";
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+ reg = <0x0 0x1ee0000 0x0 0x10000>;
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+ };
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+
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+ ifc: ifc@1530000 {
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+ compatible = "fsl,ifc", "simple-bus";
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+ reg = <0x0 0x1530000 0x0 0x10000>;
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+ interrupts = <0 43 0x4>;
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+ };
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+
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+ esdhc: esdhc@1560000 {
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+ compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
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+ reg = <0x0 0x1560000 0x0 0x10000>;
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+ interrupts = <0 62 0x4>;
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+ clock-frequency = <0>;
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+ voltage-ranges = <1800 1800 3300 3300>;
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+ sdhci,auto-cmd12;
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+ big-endian;
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+ bus-width = <4>;
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+ };
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+
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+ dspi0: dspi@2100000 {
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+ compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0 0x2100000 0x0 0x10000>;
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+ interrupts = <0 64 0x4>;
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+ clock-names = "dspi";
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+ clocks = <&clockgen 4 0>;
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+ spi-num-chipselects = <5>;
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+ big-endian;
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+ status = "disabled";
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+ };
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+
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+ dspi1: dspi@2110000 {
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+ compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0 0x2110000 0x0 0x10000>;
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+ interrupts = <0 65 0x4>;
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+ clock-names = "dspi";
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+ clocks = <&clockgen 4 0>;
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+ spi-num-chipselects = <5>;
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+ big-endian;
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+ status = "disabled";
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+ };
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+
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+ i2c0: i2c@2180000 {
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+ compatible = "fsl,vf610-i2c";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0 0x2180000 0x0 0x10000>;
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+ interrupts = <0 56 0x4>;
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+ clock-names = "i2c";
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+ clocks = <&clockgen 4 0>;
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+ dmas = <&edma0 1 39>,
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+ <&edma0 1 38>;
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+ dma-names = "tx", "rx";
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+ status = "disabled";
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+ };
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+
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+ i2c1: i2c@2190000 {
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+ compatible = "fsl,vf610-i2c";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0 0x2190000 0x0 0x10000>;
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+ interrupts = <0 57 0x4>;
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+ clock-names = "i2c";
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+ clocks = <&clockgen 4 0>;
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+ status = "disabled";
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+ };
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+
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+ i2c2: i2c@21a0000 {
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+ compatible = "fsl,vf610-i2c";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0 0x21a0000 0x0 0x10000>;
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+ interrupts = <0 58 0x4>;
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+ clock-names = "i2c";
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+ clocks = <&clockgen 4 0>;
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+ status = "disabled";
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+ };
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+
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+ i2c3: i2c@21b0000 {
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+ compatible = "fsl,vf610-i2c";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0 0x21b0000 0x0 0x10000>;
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+ interrupts = <0 59 0x4>;
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+ clock-names = "i2c";
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+ clocks = <&clockgen 4 0>;
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+ status = "disabled";
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+ };
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+
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+ duart0: serial@21c0500 {
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+ compatible = "fsl,ns16550", "ns16550a";
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+ reg = <0x00 0x21c0500 0x0 0x100>;
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+ interrupts = <0 54 0x4>;
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+ clocks = <&clockgen 4 0>;
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+ };
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+
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+ duart1: serial@21c0600 {
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+ compatible = "fsl,ns16550", "ns16550a";
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+ reg = <0x00 0x21c0600 0x0 0x100>;
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+ interrupts = <0 54 0x4>;
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+ clocks = <&clockgen 4 0>;
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+ };
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+
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+ duart2: serial@21d0500 {
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+ compatible = "fsl,ns16550", "ns16550a";
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+ reg = <0x0 0x21d0500 0x0 0x100>;
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+ interrupts = <0 55 0x4>;
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+ clocks = <&clockgen 4 0>;
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+ };
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+
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+ duart3: serial@21d0600 {
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+ compatible = "fsl,ns16550", "ns16550a";
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+ reg = <0x0 0x21d0600 0x0 0x100>;
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+ interrupts = <0 55 0x4>;
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+ clocks = <&clockgen 4 0>;
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+ };
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+
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+ gpio1: gpio@2300000 {
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+ compatible = "fsl,ls1043a-gpio";
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+ reg = <0x0 0x2300000 0x0 0x10000>;
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+ interrupts = <0 66 0x4>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ gpio2: gpio@2310000 {
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+ compatible = "fsl,ls1043a-gpio";
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+ reg = <0x0 0x2310000 0x0 0x10000>;
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+ interrupts = <0 67 0x4>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ gpio3: gpio@2320000 {
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+ compatible = "fsl,ls1043a-gpio";
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+ reg = <0x0 0x2320000 0x0 0x10000>;
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+ interrupts = <0 68 0x4>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ gpio4: gpio@2330000 {
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+ compatible = "fsl,ls1043a-gpio";
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+ reg = <0x0 0x2330000 0x0 0x10000>;
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+ interrupts = <0 134 0x4>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ lpuart0: serial@2950000 {
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+ compatible = "fsl,ls1021a-lpuart";
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+ reg = <0x0 0x2950000 0x0 0x1000>;
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+ interrupts = <0 48 0x4>;
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+ clocks = <&clockgen 0 0>;
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+ clock-names = "ipg";
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+ status = "disabled";
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+ };
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+
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+ lpuart1: serial@2960000 {
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+ compatible = "fsl,ls1021a-lpuart";
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+ reg = <0x0 0x2960000 0x0 0x1000>;
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+ interrupts = <0 49 0x4>;
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+ clocks = <&clockgen 4 0>;
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+ clock-names = "ipg";
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+ status = "disabled";
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+ };
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+
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+ lpuart2: serial@2970000 {
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+ compatible = "fsl,ls1021a-lpuart";
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+ reg = <0x0 0x2970000 0x0 0x1000>;
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+ interrupts = <0 50 0x4>;
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+ clocks = <&clockgen 4 0>;
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+ clock-names = "ipg";
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+ status = "disabled";
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+ };
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+
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+ lpuart3: serial@2980000 {
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+ compatible = "fsl,ls1021a-lpuart";
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+ reg = <0x0 0x2980000 0x0 0x1000>;
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+ interrupts = <0 51 0x4>;
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+ clocks = <&clockgen 4 0>;
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+ clock-names = "ipg";
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+ status = "disabled";
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+ };
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+
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+ lpuart4: serial@2990000 {
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+ compatible = "fsl,ls1021a-lpuart";
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+ reg = <0x0 0x2990000 0x0 0x1000>;
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+ interrupts = <0 52 0x4>;
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+ clocks = <&clockgen 4 0>;
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+ clock-names = "ipg";
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+ status = "disabled";
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+ };
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+
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+ lpuart5: serial@29a0000 {
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+ compatible = "fsl,ls1021a-lpuart";
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+ reg = <0x0 0x29a0000 0x0 0x1000>;
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+ interrupts = <0 53 0x4>;
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+ clocks = <&clockgen 4 0>;
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+ clock-names = "ipg";
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+ status = "disabled";
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+ };
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+
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+ wdog0: wdog@2ad0000 {
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+ compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
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+ reg = <0x0 0x2ad0000 0x0 0x10000>;
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+ interrupts = <0 83 0x4>;
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+ clocks = <&clockgen 4 0>;
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+ clock-names = "wdog";
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+ big-endian;
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+ };
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+
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+ edma0: edma@2c00000 {
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+ #dma-cells = <2>;
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+ compatible = "fsl,vf610-edma";
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+ reg = <0x0 0x2c00000 0x0 0x10000>,
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+ <0x0 0x2c10000 0x0 0x10000>,
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+ <0x0 0x2c20000 0x0 0x10000>;
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+ interrupts = <0 103 0x4>,
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+ <0 103 0x4>;
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+ interrupt-names = "edma-tx", "edma-err";
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+ dma-channels = <32>;
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+ big-endian;
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+ clock-names = "dmamux0", "dmamux1";
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+ clocks = <&clockgen 4 0>,
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+ <&clockgen 4 0>;
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+ };
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+
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+ usb0: usb3@2f00000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x0 0x2f00000 0x0 0x10000>;
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+ interrupts = <0 60 0x4>;
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+ dr_mode = "host";
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+ };
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+
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+ usb1: usb3@3000000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x0 0x3000000 0x0 0x10000>;
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+ interrupts = <0 61 0x4>;
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+ dr_mode = "host";
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+ };
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+
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+ usb2: usb3@3100000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x0 0x3100000 0x0 0x10000>;
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+ interrupts = <0 63 0x4>;
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+ dr_mode = "host";
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+ };
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+
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+ sata: sata@3200000 {
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+ compatible = "fsl,ls1043a-ahci";
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+ reg = <0x0 0x3200000 0x0 0x10000>;
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+ interrupts = <0 69 0x4>;
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+ clocks = <&clockgen 4 0>;
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+ };
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+
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+ msi1: msi-controller1@1571000 {
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+ compatible = "fsl,1s1043a-msi";
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+ reg = <0x0 0x1571000 0x0 0x4>,
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+ <0x0 0x1571004 0x0 0x4>;
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+ reg-names = "msiir", "msir";
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+ msi-controller;
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+ interrupts = <0 116 0x4>;
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+ };
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+
|
|
+ msi2: msi-controller2@1572000 {
|
|
+ compatible = "fsl,1s1043a-msi";
|
|
+ reg = <0x0 0x1572000 0x0 0x4>,
|
|
+ <0x0 0x1572004 0x0 0x4>;
|
|
+ reg-names = "msiir", "msir";
|
|
+ msi-controller;
|
|
+ interrupts = <0 126 0x4>;
|
|
+ };
|
|
+
|
|
+ msi3: msi-controller3@1573000 {
|
|
+ compatible = "fsl,1s1043a-msi";
|
|
+ reg = <0x0 0x1573000 0x0 0x4>,
|
|
+ <0x0 0x1573004 0x0 0x4>;
|
|
+ reg-names = "msiir", "msir";
|
|
+ msi-controller;
|
|
+ interrupts = <0 160 0x4>;
|
|
+ };
|
|
+
|
|
+ pcie@3400000 {
|
|
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
|
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
|
+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
+ reg-names = "regs", "config";
|
|
+ interrupts = <0 118 0x4>, /* controller interrupt */
|
|
+ <0 117 0x4>; /* PME interrupt */
|
|
+ interrupt-names = "intr", "pme";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ num-lanes = <4>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&msi1>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
|
|
+ <0000 0 0 2 &gic 0 111 0x4>,
|
|
+ <0000 0 0 3 &gic 0 112 0x4>,
|
|
+ <0000 0 0 4 &gic 0 113 0x4>;
|
|
+ };
|
|
+
|
|
+ pcie@3500000 {
|
|
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
|
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
|
+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
+ reg-names = "regs", "config";
|
|
+ interrupts = <0 128 0x4>,
|
|
+ <0 127 0x4>;
|
|
+ interrupt-names = "intr", "pme";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ num-lanes = <2>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&msi2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
|
|
+ <0000 0 0 2 &gic 0 121 0x4>,
|
|
+ <0000 0 0 3 &gic 0 122 0x4>,
|
|
+ <0000 0 0 4 &gic 0 123 0x4>;
|
|
+ };
|
|
+
|
|
+ pcie@3600000 {
|
|
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
|
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
|
+ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
+ reg-names = "regs", "config";
|
|
+ interrupts = <0 162 0x4>,
|
|
+ <0 161 0x4>;
|
|
+ interrupt-names = "intr", "pme";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ num-lanes = <2>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&msi3>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
|
|
+ <0000 0 0 2 &gic 0 155 0x4>,
|
|
+ <0000 0 0 3 &gic 0 156 0x4>,
|
|
+ <0000 0 0 4 &gic 0 157 0x4>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+};
|