mirror of https://github.com/hak5/openwrt-owl.git
533 lines
14 KiB
Diff
533 lines
14 KiB
Diff
From 5f592b818a2c5731bb12137e7cffc3aa6e24ee5a Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <florian@openwrt.org>
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Date: Wed, 1 Feb 2012 09:14:09 +0000
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Subject: [PATCH 13/63] spi: add Broadcom BCM63xx SPI controller driver
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This patch adds support for the SPI controller found on the Broadcom BCM63xx
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SoCs.
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Signed-off-by: Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
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Acked-by: Grant Likely <grant.likely@secretlab.ca>
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---
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drivers/spi/Kconfig | 6 +
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drivers/spi/Makefile | 1 +
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drivers/spi/spi-bcm63xx.c | 486 +++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 493 insertions(+), 0 deletions(-)
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create mode 100644 drivers/spi/spi-bcm63xx.c
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--- a/drivers/spi/Kconfig
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+++ b/drivers/spi/Kconfig
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@@ -94,6 +94,12 @@ config SPI_AU1550
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If you say yes to this option, support will be included for the
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PSC SPI controller found on Au1550, Au1200 and Au1300 series.
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+config SPI_BCM63XX
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+ tristate "Broadcom BCM63xx SPI controller"
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+ depends on BCM63XX
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+ help
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+ Enable support for the SPI controller on the Broadcom BCM63xx SoCs.
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+
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config SPI_BITBANG
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tristate "Utilities for Bitbanging SPI masters"
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help
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--- a/drivers/spi/Makefile
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+++ b/drivers/spi/Makefile
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@@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA) += spi-altera.
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obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
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obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
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obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
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+obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
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obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o
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obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
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obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
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--- /dev/null
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+++ b/drivers/spi/spi-bcm63xx.c
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@@ -0,0 +1,486 @@
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+/*
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+ * Broadcom BCM63xx SPI controller support
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+ *
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+ * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
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+ * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * as published by the Free Software Foundation; either version 2
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+ * of the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the
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+ * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/clk.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/delay.h>
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+#include <linux/interrupt.h>
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+#include <linux/spi/spi.h>
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+#include <linux/completion.h>
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+#include <linux/err.h>
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+
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+#include <bcm63xx_dev_spi.h>
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+
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+#define PFX KBUILD_MODNAME
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+#define DRV_VER "0.1.2"
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+
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+struct bcm63xx_spi {
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+ spinlock_t lock;
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+ int stopping;
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+ struct completion done;
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+
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+ void __iomem *regs;
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+ int irq;
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+
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+ /* Platform data */
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+ u32 speed_hz;
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+ unsigned fifo_size;
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+
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+ /* Data buffers */
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+ const unsigned char *tx_ptr;
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+ unsigned char *rx_ptr;
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+
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+ /* data iomem */
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+ u8 __iomem *tx_io;
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+ const u8 __iomem *rx_io;
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+
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+ int remaining_bytes;
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+
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+ struct clk *clk;
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+ struct platform_device *pdev;
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+};
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+
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+static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
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+ unsigned int offset)
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+{
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+ return bcm_readb(bs->regs + bcm63xx_spireg(offset));
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+}
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+
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+static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
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+ unsigned int offset)
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+{
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+ return bcm_readw(bs->regs + bcm63xx_spireg(offset));
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+}
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+
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+static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
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+ u8 value, unsigned int offset)
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+{
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+ bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
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+}
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+
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+static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
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+ u16 value, unsigned int offset)
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+{
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+ bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
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+}
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+
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+static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
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+ { 20000000, SPI_CLK_20MHZ },
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+ { 12500000, SPI_CLK_12_50MHZ },
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+ { 6250000, SPI_CLK_6_250MHZ },
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+ { 3125000, SPI_CLK_3_125MHZ },
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+ { 1563000, SPI_CLK_1_563MHZ },
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+ { 781000, SPI_CLK_0_781MHZ },
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+ { 391000, SPI_CLK_0_391MHZ }
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+};
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+
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+static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
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+ struct spi_transfer *t)
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+{
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+ struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
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+ u8 bits_per_word;
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+ u8 clk_cfg, reg;
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+ u32 hz;
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+ int i;
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+
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+ bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
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+ hz = (t) ? t->speed_hz : spi->max_speed_hz;
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+ if (bits_per_word != 8) {
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+ dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
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+ __func__, bits_per_word);
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+ return -EINVAL;
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+ }
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+
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+ if (spi->chip_select > spi->master->num_chipselect) {
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+ dev_err(&spi->dev, "%s, unsupported slave %d\n",
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+ __func__, spi->chip_select);
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+ return -EINVAL;
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+ }
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+
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+ /* Find the closest clock configuration */
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+ for (i = 0; i < SPI_CLK_MASK; i++) {
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+ if (hz <= bcm63xx_spi_freq_table[i][0]) {
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+ clk_cfg = bcm63xx_spi_freq_table[i][1];
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+ break;
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+ }
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+ }
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+
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+ /* No matching configuration found, default to lowest */
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+ if (i == SPI_CLK_MASK)
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+ clk_cfg = SPI_CLK_0_391MHZ;
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+
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+ /* clear existing clock configuration bits of the register */
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+ reg = bcm_spi_readb(bs, SPI_CLK_CFG);
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+ reg &= ~SPI_CLK_MASK;
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+ reg |= clk_cfg;
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+
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+ bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
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+ dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
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+ clk_cfg, hz);
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+
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+ return 0;
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+}
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+
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+/* the spi->mode bits understood by this driver: */
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+#define MODEBITS (SPI_CPOL | SPI_CPHA)
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+
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+static int bcm63xx_spi_setup(struct spi_device *spi)
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+{
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+ struct bcm63xx_spi *bs;
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+ int ret;
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+
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+ bs = spi_master_get_devdata(spi->master);
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+
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+ if (bs->stopping)
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+ return -ESHUTDOWN;
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+
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+ if (!spi->bits_per_word)
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+ spi->bits_per_word = 8;
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+
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+ if (spi->mode & ~MODEBITS) {
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+ dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
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+ __func__, spi->mode & ~MODEBITS);
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+ return -EINVAL;
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+ }
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+
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+ ret = bcm63xx_spi_setup_transfer(spi, NULL);
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+ if (ret < 0) {
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+ dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
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+ spi->mode & ~MODEBITS);
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+ return ret;
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+ }
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+
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+ dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
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+ __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
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+
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+ return 0;
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+}
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+
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+/* Fill the TX FIFO with as many bytes as possible */
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+static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
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+{
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+ u8 size;
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+
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+ /* Fill the Tx FIFO with as many bytes as possible */
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+ size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
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+ bs->fifo_size;
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+ memcpy_toio(bs->tx_io, bs->tx_ptr, size);
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+ bs->remaining_bytes -= size;
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+}
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+
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+static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
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+{
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+ struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
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+ u16 msg_ctl;
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+ u16 cmd;
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+
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+ dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
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+ t->tx_buf, t->rx_buf, t->len);
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+
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+ /* Transmitter is inhibited */
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+ bs->tx_ptr = t->tx_buf;
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+ bs->rx_ptr = t->rx_buf;
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+ init_completion(&bs->done);
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+
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+ if (t->tx_buf) {
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+ bs->remaining_bytes = t->len;
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+ bcm63xx_spi_fill_tx_fifo(bs);
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+ }
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+
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+ /* Enable the command done interrupt which
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+ * we use to determine completion of a command */
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+ bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
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+
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+ /* Fill in the Message control register */
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+ msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
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+
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+ if (t->rx_buf && t->tx_buf)
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+ msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
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+ else if (t->rx_buf)
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+ msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
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+ else if (t->tx_buf)
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+ msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
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+
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+ bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
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+
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+ /* Issue the transfer */
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+ cmd = SPI_CMD_START_IMMEDIATE;
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+ cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
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+ cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
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+ bcm_spi_writew(bs, cmd, SPI_CMD);
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+ wait_for_completion(&bs->done);
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+
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+ /* Disable the CMD_DONE interrupt */
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+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
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+
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+ return t->len - bs->remaining_bytes;
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+}
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+
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+static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m)
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+{
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+ struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
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+ struct spi_transfer *t;
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+ int ret = 0;
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+
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+ if (unlikely(list_empty(&m->transfers)))
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+ return -EINVAL;
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+
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+ if (bs->stopping)
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+ return -ESHUTDOWN;
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+
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+ list_for_each_entry(t, &m->transfers, transfer_list) {
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+ ret += bcm63xx_txrx_bufs(spi, t);
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+ }
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+
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+ m->complete(m->context);
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+
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+ return ret;
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+}
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+
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+/* This driver supports single master mode only. Hence
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+ * CMD_DONE is the only interrupt we care about
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+ */
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+static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
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+{
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+ struct spi_master *master = (struct spi_master *)dev_id;
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+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
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+ u8 intr;
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+ u16 cmd;
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+
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+ /* Read interupts and clear them immediately */
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+ intr = bcm_spi_readb(bs, SPI_INT_STATUS);
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+ bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
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+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
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+
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+ /* A tansfer completed */
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+ if (intr & SPI_INTR_CMD_DONE) {
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+ u8 rx_tail;
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+
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+ rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
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+
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+ /* Read out all the data */
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+ if (rx_tail)
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+ memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
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+
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+ /* See if there is more data to send */
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+ if (bs->remaining_bytes > 0) {
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+ bcm63xx_spi_fill_tx_fifo(bs);
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+
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+ /* Start the transfer */
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+ bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
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+ SPI_MSG_CTL);
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+ cmd = bcm_spi_readw(bs, SPI_CMD);
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+ cmd |= SPI_CMD_START_IMMEDIATE;
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+ cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
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+ bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
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+ bcm_spi_writew(bs, cmd, SPI_CMD);
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+ } else {
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+ complete(&bs->done);
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+ }
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+ }
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+
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+ return IRQ_HANDLED;
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+}
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+
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+
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+static int __devinit bcm63xx_spi_probe(struct platform_device *pdev)
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+{
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+ struct resource *r;
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+ struct device *dev = &pdev->dev;
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+ struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
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+ int irq;
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+ struct spi_master *master;
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+ struct clk *clk;
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+ struct bcm63xx_spi *bs;
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+ int ret;
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+
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+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ if (!r) {
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+ dev_err(dev, "no iomem\n");
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+ ret = -ENXIO;
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+ goto out;
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+ }
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+
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+ irq = platform_get_irq(pdev, 0);
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+ if (irq < 0) {
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+ dev_err(dev, "no irq\n");
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+ ret = -ENXIO;
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+ goto out;
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+ }
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+
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+ clk = clk_get(dev, "spi");
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+ if (IS_ERR(clk)) {
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+ dev_err(dev, "no clock for device\n");
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+ ret = PTR_ERR(clk);
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+ goto out;
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+ }
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+
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+ master = spi_alloc_master(dev, sizeof(*bs));
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+ if (!master) {
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+ dev_err(dev, "out of memory\n");
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+ ret = -ENOMEM;
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+ goto out_clk;
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+ }
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+
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+ bs = spi_master_get_devdata(master);
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+ init_completion(&bs->done);
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+
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+ platform_set_drvdata(pdev, master);
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+ bs->pdev = pdev;
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+
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+ if (!devm_request_mem_region(&pdev->dev, r->start,
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+ resource_size(r), PFX)) {
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+ dev_err(dev, "iomem request failed\n");
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+ ret = -ENXIO;
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+ goto out_err;
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+ }
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+
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+ bs->regs = devm_ioremap_nocache(&pdev->dev, r->start,
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+ resource_size(r));
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+ if (!bs->regs) {
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+ dev_err(dev, "unable to ioremap regs\n");
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+ ret = -ENOMEM;
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+ goto out_err;
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+ }
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+
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+ bs->irq = irq;
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+ bs->clk = clk;
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+ bs->fifo_size = pdata->fifo_size;
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+
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+ ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
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+ pdev->name, master);
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+ if (ret) {
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+ dev_err(dev, "unable to request irq\n");
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+ goto out_err;
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+ }
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+
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+ master->bus_num = pdata->bus_num;
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+ master->num_chipselect = pdata->num_chipselect;
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+ master->setup = bcm63xx_spi_setup;
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+ master->transfer = bcm63xx_transfer;
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+ bs->speed_hz = pdata->speed_hz;
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+ bs->stopping = 0;
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+ bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
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+ bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
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+ spin_lock_init(&bs->lock);
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+
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+ /* Initialize hardware */
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+ clk_enable(bs->clk);
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+ bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
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+
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+ /* register and we are done */
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+ ret = spi_register_master(master);
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+ if (ret) {
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+ dev_err(dev, "spi register failed\n");
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+ goto out_clk_disable;
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+ }
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+
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+ dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
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+ r->start, irq, bs->fifo_size, DRV_VER);
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+
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+ return 0;
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+
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+out_clk_disable:
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+ clk_disable(clk);
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+out_err:
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+ platform_set_drvdata(pdev, NULL);
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+ spi_master_put(master);
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|
+out_clk:
|
|
+ clk_put(clk);
|
|
+out:
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static int __devexit bcm63xx_spi_remove(struct platform_device *pdev)
|
|
+{
|
|
+ struct spi_master *master = platform_get_drvdata(pdev);
|
|
+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
|
|
+
|
|
+ /* reset spi block */
|
|
+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
|
|
+ spin_lock(&bs->lock);
|
|
+ bs->stopping = 1;
|
|
+
|
|
+ /* HW shutdown */
|
|
+ clk_disable(bs->clk);
|
|
+ clk_put(bs->clk);
|
|
+
|
|
+ spin_unlock(&bs->lock);
|
|
+ platform_set_drvdata(pdev, 0);
|
|
+ spi_unregister_master(master);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_PM
|
|
+static int bcm63xx_spi_suspend(struct device *dev)
|
|
+{
|
|
+ struct spi_master *master =
|
|
+ platform_get_drvdata(to_platform_device(dev));
|
|
+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
|
|
+
|
|
+ clk_disable(bs->clk);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcm63xx_spi_resume(struct device *dev)
|
|
+{
|
|
+ struct spi_master *master =
|
|
+ platform_get_drvdata(to_platform_device(dev));
|
|
+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
|
|
+
|
|
+ clk_enable(bs->clk);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
|
|
+ .suspend = bcm63xx_spi_suspend,
|
|
+ .resume = bcm63xx_spi_resume,
|
|
+};
|
|
+
|
|
+#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops)
|
|
+#else
|
|
+#define BCM63XX_SPI_PM_OPS NULL
|
|
+#endif
|
|
+
|
|
+static struct platform_driver bcm63xx_spi_driver = {
|
|
+ .driver = {
|
|
+ .name = "bcm63xx-spi",
|
|
+ .owner = THIS_MODULE,
|
|
+ .pm = BCM63XX_SPI_PM_OPS,
|
|
+ },
|
|
+ .probe = bcm63xx_spi_probe,
|
|
+ .remove = __devexit_p(bcm63xx_spi_remove),
|
|
+};
|
|
+
|
|
+module_platform_driver(bcm63xx_spi_driver);
|
|
+
|
|
+MODULE_ALIAS("platform:bcm63xx_spi");
|
|
+MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
|
|
+MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
|
|
+MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
|
|
+MODULE_LICENSE("GPL");
|