mirror of https://github.com/hak5/openwrt-owl.git
132 lines
4.1 KiB
Diff
132 lines
4.1 KiB
Diff
From dcfe3dd46242050f100162dce2bcad24d2c942c6 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Sat, 17 Aug 2013 19:31:42 +0200
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Subject: [PATCH] rt2x00: rt2800lib: fix beacon generation on RT3593
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On the RT3593 chipset, the beacon registers are located
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in the high 8KB part of the shared memory.
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The high part of the shared memory is only accessible
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if it is explicitly selected. Add a helper function
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in order to be able to control the SHR_MSEL bit in
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the PBF_SYS_CTRL register. Also add a few more helper
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functions and use those to select the correct part of
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the shared memory before and after accessing the beacon
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registers.
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The base addresses of the beacon registers are also
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different from the actually used values, so fix the
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'rt2800_hw_beacon_base' function to return the correct
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values.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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Changes since v1: ---
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---
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drivers/net/wireless/ralink/rt2x00/rt2800.h | 3 +++
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drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 44 +++++++++++++++++++++++++++++++
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2 files changed, 47 insertions(+)
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--- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
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+++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
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@@ -574,6 +574,7 @@
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#define PBF_SYS_CTRL 0x0400
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#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
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#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
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+#define PBF_SYS_CTRL_SHR_MSEL FIELD32(0x00080000)
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/*
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* HOST-MCU shared memory
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@@ -2026,6 +2027,8 @@ struct mac_iveiv_entry {
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(((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
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(HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
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+#define HW_BEACON_BASE_HIGH(__index) (0x4000 + (__index) * 512)
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+
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#define BEACON_BASE_TO_OFFSET(_base) (((_base) - 0x4000) / 64)
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/*
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--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
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+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
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@@ -82,6 +82,39 @@ static inline bool rt2800_is_305x_soc(st
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return false;
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}
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+static inline void rt2800_shared_mem_select(struct rt2x00_dev *rt2x00dev,
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+ bool high)
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+{
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+ u32 reg;
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+
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+ if (WARN_ON_ONCE(!rt2800_has_high_shared_mem(rt2x00dev)))
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+ return;
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+
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+ rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®);
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+ rt2x00_set_field32(®, PBF_SYS_CTRL_SHR_MSEL, high);
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+ rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
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+}
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+
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+static inline bool rt2800_beacon_uses_high_mem(struct rt2x00_dev *rt2x00dev)
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+{
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+ if (rt2x00_rt(rt2x00dev, RT3593))
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+ return true;
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+
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+ return false;
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+}
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+
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+static inline void rt2800_select_beacon_mem(struct rt2x00_dev *rt2x00dev)
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+{
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+ if (rt2800_beacon_uses_high_mem(rt2x00dev))
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+ rt2800_shared_mem_select(rt2x00dev, true);
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+}
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+
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+static inline void rt2800_deselect_beacon_mem(struct rt2x00_dev *rt2x00dev)
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+{
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+ if (rt2800_beacon_uses_high_mem(rt2x00dev))
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+ rt2800_shared_mem_select(rt2x00dev, false);
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+}
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+
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static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
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const unsigned int word, const u8 value)
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{
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@@ -948,6 +981,9 @@ EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
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static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
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unsigned int index)
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{
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+ if (rt2x00_rt(rt2x00dev, RT3593))
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+ return HW_BEACON_BASE_HIGH(index);
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+
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return HW_BEACON_BASE(index);
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}
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@@ -1046,8 +1082,12 @@ void rt2800_write_beacon(struct queue_en
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beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
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rt2800_shared_mem_lock(rt2x00dev);
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+
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+ rt2800_select_beacon_mem(rt2x00dev);
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rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
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entry->skb->len + padding_len);
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+ rt2800_deselect_beacon_mem(rt2x00dev);
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+
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rt2800_shared_mem_unlock(rt2x00dev);
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__set_bit(ENTRY_BCN_ENABLED, &entry->flags);
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@@ -1080,6 +1120,8 @@ static inline void rt2800_clear_beacon_r
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rt2800_shared_mem_lock(rt2x00dev);
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+ rt2800_select_beacon_mem(rt2x00dev);
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+
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/*
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* For the Beacon base registers we only need to clear
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* the whole TXWI which (when set to 0) will invalidate
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@@ -1088,6 +1130,8 @@ static inline void rt2800_clear_beacon_r
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for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
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rt2800_register_write(rt2x00dev, beacon_base + i, 0);
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+ rt2800_deselect_beacon_mem(rt2x00dev);
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+
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rt2800_shared_mem_unlock(rt2x00dev);
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}
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