mirror of https://github.com/hak5/openwrt-owl.git
129 lines
3.4 KiB
Diff
129 lines
3.4 KiB
Diff
From 0643a93746775da2189ab0afd8f748afcaa791c5 Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Fri, 7 Feb 2014 16:21:49 +0100
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Subject: [PATCH] clk: sunxi: Add support for USB clock-register reset bits
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The usb-clk register is special in that it not only contains clk gate bits,
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but also has a few reset bits. This commit adds support for this by allowing
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gates type sunxi clks to also register a reset controller.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
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Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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---
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drivers/clk/sunxi/clk-sunxi.c | 71 +++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 71 insertions(+)
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--- a/drivers/clk/sunxi/clk-sunxi.c
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+++ b/drivers/clk/sunxi/clk-sunxi.c
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@@ -18,6 +18,7 @@
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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+#include <linux/reset-controller.h>
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#include "clk-factors.h"
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@@ -688,6 +689,59 @@ static void __init sunxi_divider_clk_set
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/**
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+ * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
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+ */
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+
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+struct gates_reset_data {
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+ void __iomem *reg;
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+ spinlock_t *lock;
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+ struct reset_controller_dev rcdev;
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+};
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+
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+static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
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+ unsigned long id)
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+{
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+ struct gates_reset_data *data = container_of(rcdev,
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+ struct gates_reset_data,
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+ rcdev);
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+ unsigned long flags;
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+ u32 reg;
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+
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+ spin_lock_irqsave(data->lock, flags);
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+
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+ reg = readl(data->reg);
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+ writel(reg & ~BIT(id), data->reg);
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+
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+ spin_unlock_irqrestore(data->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
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+ unsigned long id)
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+{
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+ struct gates_reset_data *data = container_of(rcdev,
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+ struct gates_reset_data,
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+ rcdev);
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+ unsigned long flags;
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+ u32 reg;
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+
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+ spin_lock_irqsave(data->lock, flags);
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+
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+ reg = readl(data->reg);
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+ writel(reg | BIT(id), data->reg);
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+
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+ spin_unlock_irqrestore(data->lock, flags);
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+
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+ return 0;
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+}
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+
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+static struct reset_control_ops sunxi_gates_reset_ops = {
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+ .assert = sunxi_gates_reset_assert,
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+ .deassert = sunxi_gates_reset_deassert,
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+};
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+
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+/**
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* sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
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*/
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@@ -695,6 +749,7 @@ static void __init sunxi_divider_clk_set
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struct gates_data {
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DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
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+ u32 reset_mask;
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};
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static const struct gates_data sun4i_axi_gates_data __initconst = {
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@@ -765,6 +820,7 @@ static void __init sunxi_gates_clk_setup
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struct gates_data *data)
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{
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struct clk_onecell_data *clk_data;
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+ struct gates_reset_data *reset_data;
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const char *clk_parent;
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const char *clk_name;
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void *reg;
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@@ -808,6 +864,21 @@ static void __init sunxi_gates_clk_setup
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clk_data->clk_num = i;
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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+
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+ /* Register a reset controler for gates with reset bits */
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+ if (data->reset_mask == 0)
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+ return;
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+
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+ reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
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+ if (!reset_data)
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+ return;
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+
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+ reset_data->reg = reg;
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+ reset_data->lock = &clk_lock;
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+ reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
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+ reset_data->rcdev.ops = &sunxi_gates_reset_ops;
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+ reset_data->rcdev.of_node = node;
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+ reset_controller_register(&reset_data->rcdev);
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}
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