mirror of https://github.com/hak5/openwrt-owl.git
73 lines
2.6 KiB
Diff
73 lines
2.6 KiB
Diff
From 0262abfaac71799e3688285f1f30bead42b8ff7e Mon Sep 17 00:00:00 2001
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From: cbeytas <cbeytas@shaw.ca>
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Date: Mon, 24 Jun 2013 00:05:40 -0400
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Subject: [PATCH 020/114] Perform I2C combined transactions when possible
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Perform I2C combined transactions whenever possible, within the
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restrictions of the Broadcomm Serial Controller.
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Disable DONE interrupt during TA poll
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Prevent interrupt from being triggered if poll is missed and transfer
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starts and finishes.
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i2c: Make combined transactions optional and disabled by default
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---
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drivers/i2c/busses/i2c-bcm2708.c | 31 ++++++++++++++++++++++++++++++-
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1 file changed, 30 insertions(+), 1 deletion(-)
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--- a/drivers/i2c/busses/i2c-bcm2708.c
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+++ b/drivers/i2c/busses/i2c-bcm2708.c
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@@ -74,6 +74,9 @@ static unsigned int baudrate = CONFIG_I2
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module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
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MODULE_PARM_DESC(baudrate, "The I2C baudrate");
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+static bool combined = false;
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+module_param(combined, bool, 0644);
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+MODULE_PARM_DESC(combined, "Use combined transactions");
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struct bcm2708_i2c {
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struct i2c_adapter adapter;
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@@ -150,7 +153,7 @@ static inline void bcm2708_bsc_fifo_fill
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static inline void bcm2708_bsc_setup(struct bcm2708_i2c *bi)
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{
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unsigned long bus_hz;
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- u32 cdiv;
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+ u32 cdiv, s;
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u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1;
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bus_hz = clk_get_rate(bi->clk);
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@@ -166,6 +169,32 @@ static inline void bcm2708_bsc_setup(str
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bcm2708_wr(bi, BSC_DIV, cdiv);
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bcm2708_wr(bi, BSC_A, bi->msg->addr);
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bcm2708_wr(bi, BSC_DLEN, bi->msg->len);
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+ if (combined)
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+ {
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+ /* Do the next two messages meet combined transaction criteria?
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+ - Current message is a write, next message is a read
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+ - Both messages to same slave address
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+ - Write message can fit inside FIFO (16 bytes or less) */
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+ if ( (bi->nmsgs > 1) &&
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+ !(bi->msg[0].flags & I2C_M_RD) && (bi->msg[1].flags & I2C_M_RD) &&
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+ (bi->msg[0].addr == bi->msg[1].addr) && (bi->msg[0].len <= 16)) {
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+ /* Fill FIFO with entire write message (16 byte FIFO) */
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+ while (bi->pos < bi->msg->len)
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+ bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]);
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+ /* Start write transfer (no interrupts, don't clear FIFO) */
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+ bcm2708_wr(bi, BSC_C, BSC_C_I2CEN | BSC_C_ST);
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+ /* poll for transfer start bit (should only take 1-20 polls) */
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+ do {
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+ s = bcm2708_rd(bi, BSC_S);
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+ } while (!(s & (BSC_S_TA | BSC_S_ERR | BSC_S_CLKT | BSC_S_DONE)));
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+ /* Send next read message before the write transfer finishes. */
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+ bi->nmsgs--;
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+ bi->msg++;
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+ bi->pos = 0;
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+ bcm2708_wr(bi, BSC_DLEN, bi->msg->len);
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+ c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_INTR | BSC_C_ST | BSC_C_READ;
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+ }
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+ }
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bcm2708_wr(bi, BSC_C, c);
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}
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