mirror of https://github.com/hak5/openwrt-owl.git
278 lines
7.1 KiB
Diff
278 lines
7.1 KiB
Diff
--- a/src/drv_mei_cpe_common.c
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+++ b/src/drv_mei_cpe_common.c
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@@ -19,7 +19,6 @@
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/* get at first the driver configuration */
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#include "drv_mei_cpe_config.h"
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-#include "ifx_types.h"
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#include "drv_mei_cpe_os.h"
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#include "drv_mei_cpe_dbg.h"
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--- a/src/drv_mei_cpe_linux.h
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+++ b/src/drv_mei_cpe_linux.h
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@@ -51,12 +51,6 @@
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#include <linux/poll.h>
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#include <linux/types.h>
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-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))
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- #include <asm/ifx/ifx_types.h>
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-#else
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- #include <ifx_types.h>
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-#endif
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-
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#endif /* #if (MEI_DRV_IFXOS_ENABLE == 0)*/
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/* ============================================================================
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--- a/src/drv_mei_cpe_linux.c
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+++ b/src/drv_mei_cpe_linux.c
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@@ -98,6 +98,8 @@
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#include "drv_mei_cpe_api_atm_ptm_intern.h"
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+#include <lantiq_soc.h>
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+
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/* ===================================
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extern function declarations
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=================================== */
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@@ -1783,7 +1785,9 @@ static int __init MEI_module_init (void)
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return (result);
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}
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+#if 0
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ppa_callback_set(LTQ_MEI_SHOWTIME_CHECK, (void *)ltq_mei_atm_showtime_check);
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+#endif
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return 0;
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}
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@@ -1963,7 +1967,9 @@ static void MEI_module_exit (void)
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("MEI_DRV: Chipset Basic Exit failed" MEI_DRV_CRLF));
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}
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+#if 0
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ppa_callback_set(LTQ_MEI_SHOWTIME_CHECK, (void *)NULL);
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+#endif
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/* touch one time this variable to avoid that the linker will remove it */
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debug_level = MEI_DRV_PRN_LEVEL_OFF;
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@@ -2120,21 +2126,32 @@ static int MEI_InitModuleBasics(void)
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}
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
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+
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+#define PMU_DFE BIT(9)
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+
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static int MEI_SysClkEnable(struct clk *clk)
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{
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+#if 0
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if (IS_ERR(clk))
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return -1;
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clk_enable(clk);
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+#else
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+ ltq_pmu_enable(PMU_DFE);
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+#endif
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return 0;
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}
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static int MEI_SysClkDisable(struct clk *clk)
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{
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+#if 0
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if (IS_ERR(clk))
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return -1;
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clk_disable(clk);
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clk_put(clk);
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+#else
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+ ltq_pmu_disable(PMU_DFE);
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+#endif
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return 0;
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}
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@@ -2454,11 +2471,15 @@ IFX_int32_t MEI_IoctlInitDevice(
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pMeiDev->eModePoll = e_MEI_DEV_ACCESS_MODE_IRQ;
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pMeiDev->intMask = ME_ARC2ME_INTERRUPT_UNMASK_ALL;
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+#if 1
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+ virq = (IFX_uint32_t)pInitDev->usedIRQ;
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+#else
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))
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virq = (IFX_uint32_t)pInitDev->usedIRQ;
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#else
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virq = irq_create_mapping(NULL, (IFX_uint32_t)pInitDev->usedIRQ);
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#endif
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+#endif
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pTmpXCntrl = MEI_VrxXDevToIrqListAdd(
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MEI_DRV_LINENUM_GET(pMeiDev),
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--- a/src/drv_mei_cpe_api_atm_ptm_intern.c
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+++ b/src/drv_mei_cpe_api_atm_ptm_intern.c
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@@ -193,6 +193,51 @@ int ifx_mei_atm_led_blink(void)
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return IFX_SUCCESS;
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}
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+#if MEI_MAX_DFE_CHAN_DEVICES > 1
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+#error "Compat functions do not support MEI_MAX_DFE_CHAN_DEVICES > 1 yet"
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+#else
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+int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
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+int (*ifx_mei_atm_showtime_exit)(void) = NULL;
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+
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+ltq_ifx_mei_atm_showtime_enter_compat(IFX_uint8_t dslLineNum,
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+ struct port_cell_info *cellInfo,
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+ void *xdata) {
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+ if (ifx_mei_atm_showtime_enter)
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+ return ifx_mei_atm_showtime_enter(cellInfo, xdata);
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+
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+ return -e_MEI_ERR_OP_FAILED;
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+}
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+
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+ltq_ifx_mei_atm_showtime_exit_compat(IFX_uint8_t dslLineNum) {
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+ if (ifx_mei_atm_showtime_exit)
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+ return ifx_mei_atm_showtime_exit();
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+
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+ return -e_MEI_ERR_OP_FAILED;
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+}
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+
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+void* ppa_callback_get(e_ltq_mei_cb_type type) {
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+ switch (type) {
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+ case LTQ_MEI_SHOWTIME_ENTER:
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+ return <q_ifx_mei_atm_showtime_enter_compat;
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+ case LTQ_MEI_SHOWTIME_EXIT:
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+ return <q_ifx_mei_atm_showtime_exit_compat;
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+ break;
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+ }
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+
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+ BUG();
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+}
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+
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+int ifx_mei_atm_showtime_check(int *is_showtime,
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+ struct port_cell_info *port_cell,
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+ void **xdata_addr) {
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+ return ltq_mei_atm_showtime_check(0, is_showtime, port_cell, xdata_addr);
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+}
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+
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+EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
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+EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
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+EXPORT_SYMBOL(ifx_mei_atm_showtime_check);
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+#endif
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+
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EXPORT_SYMBOL (MEI_InternalXtmSwhowtimeEntrySignal);
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EXPORT_SYMBOL (MEI_InternalXtmSwhowtimeExitSignal);
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EXPORT_SYMBOL(ifx_mei_atm_led_blink);
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--- a/src/drv_mei_cpe_api_atm_ptm_intern.h
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+++ b/src/drv_mei_cpe_api_atm_ptm_intern.h
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@@ -21,7 +21,6 @@
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#include "drv_mei_cpe_config.h"
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#include "drv_mei_cpe_interface.h"
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-#include <net/ppa_stack_al.h>
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#if (MEI_EXPORT_INTERNAL_API == 1) && (MEI_DRV_ATM_PTM_INTERFACE_ENABLE == 1)
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@@ -42,8 +41,20 @@ extern IFX_int32_t MEI_InternalXtmSwhowt
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MEI_DYN_CNTRL_T *pMeiDynCntrl,
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MEI_XTM_ShowtimeExit_t *pArgXtm);
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+#if 1
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+typedef enum {
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+ LTQ_MEI_SHOWTIME_ENTER,
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+ LTQ_MEI_SHOWTIME_EXIT
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+} e_ltq_mei_cb_type;
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+
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+typedef void (*ltq_mei_atm_showtime_enter_t)(IFX_uint8_t, struct port_cell_info *, void *);
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+typedef void (*ltq_mei_atm_showtime_exit_t)(IFX_uint8_t);
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+
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+void* ppa_callback_get(e_ltq_mei_cb_type type);
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+#else
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extern int ppa_callback_set(e_ltq_mei_cb_type type, void *func);
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extern void* ppa_callback_get(e_ltq_mei_cb_type type);
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+#endif
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int ltq_mei_atm_showtime_check (
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const unsigned char line_idx,
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--- a/src/drv_mei_cpe_device_vrx.c
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+++ b/src/drv_mei_cpe_device_vrx.c
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@@ -27,13 +27,6 @@
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#include "drv_mei_cpe_mei_interface.h"
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#include "drv_mei_cpe_api.h"
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-#if defined(LINUX)
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-# if (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))
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-# include "ifx_pcie.h"
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-# else
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-# include "lantiq_pcie.h"
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-# endif
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-#endif /* #if defined(LINUX)*/
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IFX_int32_t MEI_GPIntProcess(MEI_MeiRegVal_t processInt, MEI_DEV_T *pMeiDev)
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{
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@@ -81,6 +74,7 @@ IFX_int32_t MEI_GetChipInfo(MEI_DEV_T *p
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*/
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IFX_int32_t MEI_VR10_PcieEntitiesCheck(IFX_uint8_t nEntityNum)
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{
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+#if 0
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IFX_uint32_t pcie_entitiesNum;
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/* get information from pcie driver */
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@@ -101,6 +95,9 @@ IFX_int32_t MEI_VR10_PcieEntitiesCheck(I
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}
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return IFX_SUCCESS;
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+#else
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+ return IFX_ERROR;
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+#endif
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}
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/**
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@@ -115,6 +112,7 @@ IFX_int32_t MEI_VR10_PcieEntitiesCheck(I
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*/
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IFX_int32_t MEI_VR10_PcieEntityInit(MEI_MEI_DRV_CNTRL_T *pMeiDrvCntrl)
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{
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+#if 0
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IFX_uint8_t entityNum;
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ifx_pcie_ep_dev_t MEI_pcie_ep_dev;
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@@ -137,6 +135,9 @@ IFX_int32_t MEI_VR10_PcieEntityInit(MEI_
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pMeiDrvCntrl->MEI_pcie_irq = MEI_pcie_ep_dev.irq;
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return IFX_SUCCESS;
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+#else
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+ return IFX_ERROR;
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+#endif
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}
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/**
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@@ -151,6 +152,7 @@ IFX_int32_t MEI_VR10_PcieEntityInit(MEI_
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*/
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IFX_int32_t MEI_VR10_PcieEntityFree(IFX_uint8_t entityNum)
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{
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+#if 0
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if (ifx_pcie_ep_dev_info_release(entityNum))
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{
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PRN_ERR_USR_NL( MEI_DRV, MEI_DRV_PRN_LEVEL_ERR,
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@@ -160,6 +162,9 @@ IFX_int32_t MEI_VR10_PcieEntityFree(IFX_
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}
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return IFX_SUCCESS;
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+#else
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+ return IFX_ERROR;
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+#endif
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}
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/**
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@@ -174,6 +179,7 @@ IFX_int32_t MEI_VR10_PcieEntityFree(IFX_
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*/
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IFX_int32_t MEI_VR10_InternalInitDevice(MEI_DYN_CNTRL_T *pMeiDynCntrl)
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{
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+#if 0
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IFX_int32_t retVal;
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IOCTL_MEI_devInit_t InitDev;
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MEI_DEV_T *pMeiDev = pMeiDynCntrl->pMeiDev;
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@@ -198,5 +204,8 @@ IFX_int32_t MEI_VR10_InternalInitDevice(
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*MEI_GPIO_U32REG(GPIO_P0_ALSEL1) &= ~((1 << 0) | (1 << 3) | (1 << 8));
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return IFX_SUCCESS;
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+#else
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+ return IFX_ERROR;
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+#endif
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}
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