mirror of https://github.com/hak5/openwrt-owl.git
450 lines
12 KiB
Diff
450 lines
12 KiB
Diff
From 22345cc059de4a6ea1dc7657dd6ad86ca16a8814 Mon Sep 17 00:00:00 2001
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From: Oliver Schinagl <oliver@schinagl.nl>
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Date: Tue, 3 Dec 2013 12:07:01 +0100
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Subject: [PATCH] ARM: sunxi: Add ahci-sunxi driver for the Allwinner SUNXi
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SoCs sata
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This patch adds support for the ahci sata controler found on Allwinner A10
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and A20 SoCs.
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Orignally written by Olliver Schinagl using the approach of having a platform
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device which probe method creates a new child platform device which gets
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driven by ahci_platform.c, as done by ahci_imx.c .
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Given that almost all functionality already is shared through libahci /
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ata-core, and that ahci_platform.c cannot cleanly handle somewhat more complex
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platform specific ahci cases, such as the sunxi case, it was refactored into
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a stand-alone platform driver by Hans de Goede.
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Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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.../devicetree/bindings/ata/ahci-sunxi.txt | 24 ++
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drivers/ata/Kconfig | 9 +
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drivers/ata/Makefile | 1 +
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drivers/ata/ahci_sunxi.c | 349 +++++++++++++++++++++
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4 files changed, 383 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/ata/ahci-sunxi.txt
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create mode 100644 drivers/ata/ahci_sunxi.c
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diff --git a/Documentation/devicetree/bindings/ata/ahci-sunxi.txt b/Documentation/devicetree/bindings/ata/ahci-sunxi.txt
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new file mode 100644
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index 0000000..0792fa5
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/ata/ahci-sunxi.txt
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@@ -0,0 +1,24 @@
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+Allwinner SUNXI AHCI SATA Controller
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+
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+SATA nodes are defined to describe on-chip Serial ATA controllers.
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+Each SATA controller should have its own node.
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+
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+Required properties:
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+- compatible : compatible list, contains "allwinner,sun4i-a10-ahci"
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+- reg : <registers mapping>
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+- interrupts : <interrupt mapping for AHCI IRQ>
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+- clocks : clocks for ACHI
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+- clock-names : clock names for AHCI
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+
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+Optional properties:
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+- pwr-supply : regulator to control the power supply GPIO
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+
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+Example:
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+ ahci@01c18000 {
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+ compatible = "allwinner,sun4i-a10-ahci";
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+ reg = <0x01c18000 0x1000>;
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+ interrupts = <0 56 1>;
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+ clocks = <&ahb_gates 25>, <&pll6 0>;
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+ clock-names = "ahb_sata", "pll6_sata";
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+ pwr-supply = <®_ahci_5v>;
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+ };
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diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
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index 4e73772..3c80bbe 100644
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--- a/drivers/ata/Kconfig
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+++ b/drivers/ata/Kconfig
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@@ -106,6 +106,15 @@ config AHCI_IMX
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If unsure, say N.
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+config AHCI_SUNXI
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+ tristate "Allwinner sunxi AHCI SATA support"
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+ depends on ARCH_SUNXI
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+ help
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+ This option enables support for the Allwinner sunxi SoC's
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+ onboard AHCI SATA.
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+
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+ If unsure, say N.
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+
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config SATA_FSL
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tristate "Freescale 3.0Gbps SATA support"
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depends on FSL_SOC
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diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
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index 46518c6..956abc3 100644
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--- a/drivers/ata/Makefile
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+++ b/drivers/ata/Makefile
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@@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
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obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
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obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
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obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
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+obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o
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# SFF w/ custom DMA
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obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
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diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
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new file mode 100644
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index 0000000..22d3972
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--- /dev/null
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+++ b/drivers/ata/ahci_sunxi.c
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@@ -0,0 +1,349 @@
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+/*
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+ * Allwinner sunxi AHCI SATA platform driver
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+ * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
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+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
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+ *
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+ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
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+ * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
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+ * Daniel Wang <danielwang@allwinnertech.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/errno.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/of_device.h>
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+#include <linux/platform_device.h>
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+#include <linux/regulator/consumer.h>
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+#include "ahci.h"
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+
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+#define AHCI_BISTAFR 0x00a0
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+#define AHCI_BISTCR 0x00a4
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+#define AHCI_BISTFCTR 0x00a8
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+#define AHCI_BISTSR 0x00ac
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+#define AHCI_BISTDECR 0x00b0
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+#define AHCI_DIAGNR0 0x00b4
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+#define AHCI_DIAGNR1 0x00b8
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+#define AHCI_OOBR 0x00bc
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+#define AHCI_PHYCS0R 0x00c0
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+#define AHCI_PHYCS1R 0x00c4
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+#define AHCI_PHYCS2R 0x00c8
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+#define AHCI_TIMER1MS 0x00e0
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+#define AHCI_GPARAM1R 0x00e8
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+#define AHCI_GPARAM2R 0x00ec
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+#define AHCI_PPARAMR 0x00f0
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+#define AHCI_TESTR 0x00f4
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+#define AHCI_VERSIONR 0x00f8
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+#define AHCI_IDR 0x00fc
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+#define AHCI_RWCR 0x00fc
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+#define AHCI_P0DMACR 0x0170
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+#define AHCI_P0PHYCR 0x0178
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+#define AHCI_P0PHYSR 0x017c
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+
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+struct sunxi_ahci {
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+ struct ahci_host_priv hpriv;
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+ struct regulator *pwr;
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+ struct clk *sata_clk;
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+ struct clk *ahb_clk;
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+};
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+
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+static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
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+{
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+ u32 reg_val;
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+
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+ reg_val = readl(reg);
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+ reg_val &= ~(clr_val);
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+ writel(reg_val, reg);
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+}
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+
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+static void sunxi_setbits(void __iomem *reg, u32 set_val)
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+{
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+ u32 reg_val;
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+
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+ reg_val = readl(reg);
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+ reg_val |= set_val;
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+ writel(reg_val, reg);
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+}
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+
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+static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
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+{
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+ u32 reg_val;
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+
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+ reg_val = readl(reg);
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+ reg_val &= ~(clr_val);
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+ reg_val |= set_val;
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+ writel(reg_val, reg);
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+}
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+
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+static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
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+{
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+ return (readl(reg) >> shift) & mask;
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+}
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+
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+static int sunxi_ahci_phy_init(struct device *dev, void __iomem *reg_base)
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+{
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+ u32 reg_val;
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+ int timeout;
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+
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+ /* This magic is from the original code */
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+ writel(0, reg_base + AHCI_RWCR);
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+ mdelay(5);
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+
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+ sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
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+ sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
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+ (0x7 << 24),
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+ (0x5 << 24) | BIT(23) | BIT(18));
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+ sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
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+ (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
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+ (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
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+ sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
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+ sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
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+ sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
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+ (0x7 << 20), (0x3 << 20));
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+ sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
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+ (0x1f << 5), (0x19 << 5));
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+ mdelay(5);
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+
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+ sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
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+
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+ timeout = 0x100000;
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+ do {
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+ reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
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+ } while (--timeout && (reg_val != 0x2));
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+ if (!timeout) {
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+ dev_err(dev, "PHY power up failed.\n");
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+ return -EIO;
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+ }
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+
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+ sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
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+
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+ timeout = 0x100000;
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+ do {
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+ reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
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+ } while (--timeout && reg_val);
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+ if (!timeout) {
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+ dev_err(dev, "PHY calibration failed.\n");
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+ return -EIO;
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+ }
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+ mdelay(15);
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+
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+ writel(0x7, reg_base + AHCI_RWCR);
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+
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+ return 0;
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+}
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+
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+void sunxi_ahci_pre_start_engine(struct ata_port *ap)
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+{
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+ struct ahci_host_priv *hpriv = ap->host->private_data;
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+
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+ /* Setup DMA before DMA start */
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+ sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
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+}
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+
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+static int sunxi_ahci_enable_clks(struct sunxi_ahci *ahci)
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+{
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+ int ret;
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+
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+ ret = clk_prepare_enable(ahci->sata_clk);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_prepare_enable(ahci->ahb_clk);
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+ if (ret)
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+ clk_disable_unprepare(ahci->sata_clk);
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+
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+ return ret;
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+}
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+
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+static void sunxi_ahci_disable_clks(struct sunxi_ahci *ahci)
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+{
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+ clk_disable_unprepare(ahci->ahb_clk);
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+ clk_disable_unprepare(ahci->sata_clk);
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+}
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+
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+static void sunxi_ahci_host_stop(struct ata_host *host)
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+{
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+ struct ahci_host_priv *hpriv = host->private_data;
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+ struct sunxi_ahci *ahci = hpriv->plat_data;
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+
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+ if (!IS_ERR(ahci->pwr))
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+ regulator_disable(ahci->pwr);
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+
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+ sunxi_ahci_disable_clks(ahci);
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+}
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+
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+static struct ata_port_operations sunxi_ahci_platform_ops = {
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+ .inherits = &ahci_ops,
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+ .host_stop = sunxi_ahci_host_stop,
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+};
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+
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+static const struct ata_port_info sunxiahci_port_info = {
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+ AHCI_HFLAGS(AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
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+ AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ),
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+ .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
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+ .pio_mask = ATA_PIO4,
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+ .udma_mask = ATA_UDMA6,
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+ .port_ops = &sunxi_ahci_platform_ops,
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+};
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+
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+static struct scsi_host_template sunxi_ahci_platform_sht = {
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+ AHCI_SHT("sunxi_ahci"),
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+};
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+
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+static int sunxi_ahci_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ const struct ata_port_info *ppi[] = { &sunxiahci_port_info, NULL };
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+ struct sunxi_ahci *ahci;
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+ struct ata_host *host;
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+ int ret;
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+
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+ ahci = devm_kzalloc(&pdev->dev, sizeof(*ahci), GFP_KERNEL);
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+ if (!ahci)
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+ return -ENOMEM;
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+
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+ ahci->pwr = devm_regulator_get_optional(dev, "pwr");
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+ if (IS_ERR(ahci->pwr) && PTR_ERR(ahci->pwr) == -EPROBE_DEFER)
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+ return -EPROBE_DEFER;
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+
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+ host = ata_host_alloc_pinfo(dev, ppi, 1);
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+ if (!host)
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+ return -ENOMEM;
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+
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+ host->private_data = &ahci->hpriv;
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+ host->flags |= ATA_HOST_PARALLEL_SCAN;
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+
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+ ahci->hpriv.flags = (unsigned long)ppi[0]->private_data;
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+ ahci->hpriv.plat_data = ahci;
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+ ahci->hpriv.pre_start_engine = sunxi_ahci_pre_start_engine;
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+ ahci->hpriv.mmio = devm_ioremap_resource(dev,
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+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
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+ if (IS_ERR(ahci->hpriv.mmio))
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+ return PTR_ERR(ahci->hpriv.mmio);
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+
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+ ahci->ahb_clk = devm_clk_get(&pdev->dev, "ahb_sata");
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+ if (IS_ERR(ahci->ahb_clk))
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+ return PTR_ERR(ahci->ahb_clk);
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+
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+ ahci->sata_clk = devm_clk_get(&pdev->dev, "pll6_sata");
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+ if (IS_ERR(ahci->sata_clk))
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+ return PTR_ERR(ahci->sata_clk);
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+
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+ ret = sunxi_ahci_enable_clks(ahci);
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+ if (ret)
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+ return ret;
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+
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+ if (!IS_ERR(ahci->pwr)) {
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+ ret = regulator_enable(ahci->pwr);
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+ if (ret) {
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+ sunxi_ahci_disable_clks(ahci);
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+ return ret;
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+ }
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+ }
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+
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+ ret = sunxi_ahci_phy_init(dev, ahci->hpriv.mmio);
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+ if (ret) {
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+ sunxi_ahci_host_stop(host);
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+ return ret;
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+ }
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+
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+ ahci_save_initial_config(dev, &ahci->hpriv, 0, 0);
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+
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+ ret = ahci_reset_controller(host);
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+ if (ret) {
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+ sunxi_ahci_host_stop(host);
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+ return ret;
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+ }
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+
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+ ahci_init_controller(host);
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+ ahci_print_info(host, "sunxi");
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+
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+ ret = ata_host_activate(host, platform_get_irq(pdev, 0),
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+ ahci_interrupt, 0, &sunxi_ahci_platform_sht);
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+ if (ret)
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+ sunxi_ahci_host_stop(host);
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+
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+ return ret;
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+}
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+
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+#ifdef CONFIG_PM_SLEEP
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+static int sunxi_ahci_susp(struct device *dev)
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+{
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+ struct ata_host *host = dev_get_drvdata(dev);
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+ struct ahci_host_priv *hpriv = host->private_data;
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+ struct sunxi_ahci *ahci = hpriv->plat_data;
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+ int ret;
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+
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+ /*
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+ * AHCI spec rev1.1 section 8.3.3:
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+ * Software must disable interrupts prior to requesting a
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+ * transition of the HBA to D3 state.
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+ */
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+ sunxi_clrbits(hpriv->mmio + HOST_CTL, HOST_IRQ_EN);
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+
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+ ret = ata_host_suspend(host, PMSG_SUSPEND);
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+ if (ret)
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+ return ret;
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+
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+ sunxi_ahci_disable_clks(ahci);
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+
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+ return 0;
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+}
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+
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+static int sunxi_ahci_resume(struct device *dev)
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+{
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+ struct ata_host *host = dev_get_drvdata(dev);
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+ struct ahci_host_priv *hpriv = host->private_data;
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+ struct sunxi_ahci *ahci = hpriv->plat_data;
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+ int ret;
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+
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+ ret = sunxi_ahci_enable_clks(ahci);
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+ if (ret)
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+ return ret;
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+
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+ if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
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+ ret = ahci_reset_controller(host);
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+ if (ret)
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+ return ret;
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+
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+ ahci_init_controller(host);
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+ }
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+
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+ ata_host_resume(host);
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+
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+ return 0;
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+}
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+#endif
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+
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+static SIMPLE_DEV_PM_OPS(sunxi_ahci_pmo, sunxi_ahci_susp, sunxi_ahci_resume);
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+
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+static const struct of_device_id sunxi_ahci_of_match[] = {
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+ { .compatible = "allwinner,sun4i-a10-ahci" },
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+ { /* sentinel */ },
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+};
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+MODULE_DEVICE_TABLE(of, sunxi_ahci_of_match);
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+
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+static struct platform_driver sunxi_ahci_driver = {
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+ .probe = sunxi_ahci_probe,
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+ .remove = ata_platform_remove_one,
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+ .driver = {
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+ .name = "sunxi-ahci",
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+ .owner = THIS_MODULE,
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+ .of_match_table = sunxi_ahci_of_match,
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+ .pm = &sunxi_ahci_pmo,
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+ },
|
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+};
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+module_platform_driver(sunxi_ahci_driver);
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+
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+MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA platform driver");
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+MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>");
|
|
+MODULE_LICENSE("GPL");
|
|
--
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1.8.5.1
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|
|