mirror of https://github.com/hak5/openwrt-owl.git
136 lines
3.5 KiB
Diff
136 lines
3.5 KiB
Diff
From 5f554ea6757748c2fc45228030a20e08f6053ff7 Mon Sep 17 00:00:00 2001
|
|
From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
|
|
Date: Tue, 21 May 2013 21:28:32 -0300
|
|
Subject: [PATCH] ARM: sun4i: dt: mod0 clocks
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
This commit adds all the mod0 clocks present on sun4i to its device tree
|
|
|
|
Signed-off-by: Emilio López <emilio@elopez.com.ar>
|
|
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
---
|
|
arch/arm/boot/dts/sun4i-a10.dtsi | 105 +++++++++++++++++++++++++++++++++++++++
|
|
1 file changed, 105 insertions(+)
|
|
|
|
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
|
|
index ebacb5d..2828427e 100644
|
|
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
|
|
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
|
|
@@ -184,6 +184,111 @@
|
|
"apb1_uart4", "apb1_uart5", "apb1_uart6",
|
|
"apb1_uart7";
|
|
};
|
|
+
|
|
+ nand: nand@01c20080 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c20080 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
+
|
|
+ ms: ms@01c20084 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c20084 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
+
|
|
+ mmc0: mmc0@01c20088 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c20088 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
+
|
|
+ mmc1: mmc1@01c2008c {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c2008c 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
+
|
|
+ mmc2: mmc2@01c20090 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c20090 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
+
|
|
+ mmc3: mmc3@01c20094 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c20094 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
+
|
|
+ ts: ts@01c20098 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c20098 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
+
|
|
+ ss: ss@01c2009c {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c2009c 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
+
|
|
+ spi0: spi0@01c200a0 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c200a0 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
+
|
|
+ spi1: spi1@01c200a4 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c200a4 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
+
|
|
+ spi2: spi2@01c200a8 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c200a8 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
+
|
|
+ pata: pata@01c200ac {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c200ac 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
+
|
|
+ ir0: ir0@01c200b0 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c200b0 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
+
|
|
+ ir1: ir1@01c200b4 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c200b4 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
+
|
|
+ spi3: spi3@01c200d4 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-mod0-clk";
|
|
+ reg = <0x01c200d4 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
+ };
|
|
};
|
|
|
|
soc@01c00000 {
|
|
--
|
|
1.8.5.1
|
|
|