mirror of https://github.com/hak5/openwrt-owl.git
687 lines
21 KiB
Diff
687 lines
21 KiB
Diff
--- a/drivers/ssb/Kconfig
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+++ b/drivers/ssb/Kconfig
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@@ -168,6 +168,7 @@ config SSB_DRIVER_GIGE
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config SSB_DRIVER_GPIO
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bool "SSB GPIO driver"
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depends on SSB && GPIOLIB
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+ select IRQ_DOMAIN if SSB_EMBEDDED
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help
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Driver to provide access to the GPIO pins on the bus.
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--- a/drivers/ssb/driver_chipcommon_sflash.c
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+++ b/drivers/ssb/driver_chipcommon_sflash.c
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@@ -37,7 +37,7 @@ static const struct ssb_sflash_tbl_e ssb
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{ "M25P32", 0x15, 0x10000, 64, },
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{ "M25P64", 0x16, 0x10000, 128, },
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{ "M25FL128", 0x17, 0x10000, 256, },
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- { 0 },
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+ { NULL },
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};
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static const struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
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@@ -55,7 +55,7 @@ static const struct ssb_sflash_tbl_e ssb
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{ "SST25VF016", 0x41, 0x1000, 512, },
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{ "SST25VF032", 0x4a, 0x1000, 1024, },
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{ "SST25VF064", 0x4b, 0x1000, 2048, },
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- { 0 },
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+ { NULL },
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};
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static const struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
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@@ -66,7 +66,7 @@ static const struct ssb_sflash_tbl_e ssb
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{ "AT45DB161", 0x2c, 512, 4096, },
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{ "AT45DB321", 0x34, 512, 8192, },
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{ "AT45DB642", 0x3c, 1024, 8192, },
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- { 0 },
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+ { NULL },
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};
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static void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
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--- a/drivers/ssb/driver_gpio.c
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+++ b/drivers/ssb/driver_gpio.c
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@@ -9,16 +9,40 @@
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*/
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#include <linux/gpio.h>
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+#include <linux/irq.h>
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+#include <linux/interrupt.h>
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+#include <linux/irqdomain.h>
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#include <linux/export.h>
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#include <linux/ssb/ssb.h>
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#include "ssb_private.h"
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+
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+/**************************************************
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+ * Shared
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+ **************************************************/
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+
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static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
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{
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return container_of(chip, struct ssb_bus, gpio);
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}
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+#if IS_ENABLED(CONFIG_SSB_EMBEDDED)
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+static int ssb_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
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+{
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+ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
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+
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+ if (bus->bustype == SSB_BUSTYPE_SSB)
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+ return irq_find_mapping(bus->irq_domain, gpio);
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+ else
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+ return -EINVAL;
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+}
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+#endif
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+
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+/**************************************************
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+ * ChipCommon
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+ **************************************************/
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+
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static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
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{
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struct ssb_bus *bus = ssb_gpio_get_bus(chip);
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@@ -74,19 +98,129 @@ static void ssb_gpio_chipco_free(struct
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ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
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}
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-static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio)
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+#if IS_ENABLED(CONFIG_SSB_EMBEDDED)
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+static void ssb_gpio_irq_chipco_mask(struct irq_data *d)
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{
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- struct ssb_bus *bus = ssb_gpio_get_bus(chip);
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+ struct ssb_bus *bus = irq_data_get_irq_chip_data(d);
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+ int gpio = irqd_to_hwirq(d);
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- if (bus->bustype == SSB_BUSTYPE_SSB)
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- return ssb_mips_irq(bus->chipco.dev) + 2;
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- else
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- return -EINVAL;
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+ ssb_chipco_gpio_intmask(&bus->chipco, BIT(gpio), 0);
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+}
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+
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+static void ssb_gpio_irq_chipco_unmask(struct irq_data *d)
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+{
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+ struct ssb_bus *bus = irq_data_get_irq_chip_data(d);
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+ int gpio = irqd_to_hwirq(d);
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+ u32 val = ssb_chipco_gpio_in(&bus->chipco, BIT(gpio));
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+
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+ ssb_chipco_gpio_polarity(&bus->chipco, BIT(gpio), val);
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+ ssb_chipco_gpio_intmask(&bus->chipco, BIT(gpio), BIT(gpio));
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+}
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+
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+static struct irq_chip ssb_gpio_irq_chipco_chip = {
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+ .name = "SSB-GPIO-CC",
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+ .irq_mask = ssb_gpio_irq_chipco_mask,
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+ .irq_unmask = ssb_gpio_irq_chipco_unmask,
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+};
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+
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+static irqreturn_t ssb_gpio_irq_chipco_handler(int irq, void *dev_id)
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+{
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+ struct ssb_bus *bus = dev_id;
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+ struct ssb_chipcommon *chipco = &bus->chipco;
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+ u32 val = chipco_read32(chipco, SSB_CHIPCO_GPIOIN);
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+ u32 mask = chipco_read32(chipco, SSB_CHIPCO_GPIOIRQ);
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+ u32 pol = chipco_read32(chipco, SSB_CHIPCO_GPIOPOL);
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+ unsigned long irqs = (val ^ pol) & mask;
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+ int gpio;
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+
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+ if (!irqs)
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+ return IRQ_NONE;
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+
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+ for_each_set_bit(gpio, &irqs, bus->gpio.ngpio)
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+ generic_handle_irq(ssb_gpio_to_irq(&bus->gpio, gpio));
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+ ssb_chipco_gpio_polarity(chipco, irqs, val & irqs);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static int ssb_gpio_irq_chipco_domain_init(struct ssb_bus *bus)
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+{
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+ struct ssb_chipcommon *chipco = &bus->chipco;
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+ struct gpio_chip *chip = &bus->gpio;
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+ int gpio, hwirq, err;
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+
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+ if (bus->bustype != SSB_BUSTYPE_SSB)
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+ return 0;
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+
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+ bus->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
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+ &irq_domain_simple_ops, chipco);
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+ if (!bus->irq_domain) {
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+ err = -ENODEV;
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+ goto err_irq_domain;
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+ }
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+ for (gpio = 0; gpio < chip->ngpio; gpio++) {
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+ int irq = irq_create_mapping(bus->irq_domain, gpio);
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+
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+ irq_set_chip_data(irq, bus);
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+ irq_set_chip_and_handler(irq, &ssb_gpio_irq_chipco_chip,
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+ handle_simple_irq);
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+ }
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+
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+ hwirq = ssb_mips_irq(bus->chipco.dev) + 2;
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+ err = request_irq(hwirq, ssb_gpio_irq_chipco_handler, IRQF_SHARED,
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+ "gpio", bus);
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+ if (err)
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+ goto err_req_irq;
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+
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+ ssb_chipco_gpio_intmask(&bus->chipco, ~0, 0);
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+ chipco_set32(chipco, SSB_CHIPCO_IRQMASK, SSB_CHIPCO_IRQ_GPIO);
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+
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+ return 0;
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+
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+err_req_irq:
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+ for (gpio = 0; gpio < chip->ngpio; gpio++) {
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+ int irq = irq_find_mapping(bus->irq_domain, gpio);
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+
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+ irq_dispose_mapping(irq);
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+ }
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+ irq_domain_remove(bus->irq_domain);
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+err_irq_domain:
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+ return err;
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+}
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+
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+static void ssb_gpio_irq_chipco_domain_exit(struct ssb_bus *bus)
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+{
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+ struct ssb_chipcommon *chipco = &bus->chipco;
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+ struct gpio_chip *chip = &bus->gpio;
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+ int gpio;
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+
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+ if (bus->bustype != SSB_BUSTYPE_SSB)
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+ return;
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+
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+ chipco_mask32(chipco, SSB_CHIPCO_IRQMASK, ~SSB_CHIPCO_IRQ_GPIO);
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+ free_irq(ssb_mips_irq(bus->chipco.dev) + 2, chipco);
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+ for (gpio = 0; gpio < chip->ngpio; gpio++) {
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+ int irq = irq_find_mapping(bus->irq_domain, gpio);
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+
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+ irq_dispose_mapping(irq);
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+ }
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+ irq_domain_remove(bus->irq_domain);
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+}
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+#else
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+static int ssb_gpio_irq_chipco_domain_init(struct ssb_bus *bus)
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+{
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+ return 0;
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+}
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+
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+static void ssb_gpio_irq_chipco_domain_exit(struct ssb_bus *bus)
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+{
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}
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+#endif
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static int ssb_gpio_chipco_init(struct ssb_bus *bus)
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{
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struct gpio_chip *chip = &bus->gpio;
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+ int err;
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chip->label = "ssb_chipco_gpio";
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chip->owner = THIS_MODULE;
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@@ -96,7 +230,9 @@ static int ssb_gpio_chipco_init(struct s
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chip->set = ssb_gpio_chipco_set_value;
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chip->direction_input = ssb_gpio_chipco_direction_input;
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chip->direction_output = ssb_gpio_chipco_direction_output;
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- chip->to_irq = ssb_gpio_chipco_to_irq;
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+#if IS_ENABLED(CONFIG_SSB_EMBEDDED)
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+ chip->to_irq = ssb_gpio_to_irq;
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+#endif
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chip->ngpio = 16;
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/* There is just one SoC in one device and its GPIO addresses should be
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* deterministic to address them more easily. The other buses could get
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@@ -106,9 +242,23 @@ static int ssb_gpio_chipco_init(struct s
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else
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chip->base = -1;
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- return gpiochip_add(chip);
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+ err = ssb_gpio_irq_chipco_domain_init(bus);
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+ if (err)
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+ return err;
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+
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+ err = gpiochip_add(chip);
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+ if (err) {
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+ ssb_gpio_irq_chipco_domain_exit(bus);
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+ return err;
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+ }
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+
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+ return 0;
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}
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+/**************************************************
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+ * EXTIF
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+ **************************************************/
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+
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#ifdef CONFIG_SSB_DRIVER_EXTIF
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static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
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@@ -145,19 +295,127 @@ static int ssb_gpio_extif_direction_outp
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return 0;
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}
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-static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio)
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+#if IS_ENABLED(CONFIG_SSB_EMBEDDED)
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+static void ssb_gpio_irq_extif_mask(struct irq_data *d)
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{
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- struct ssb_bus *bus = ssb_gpio_get_bus(chip);
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+ struct ssb_bus *bus = irq_data_get_irq_chip_data(d);
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+ int gpio = irqd_to_hwirq(d);
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- if (bus->bustype == SSB_BUSTYPE_SSB)
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- return ssb_mips_irq(bus->extif.dev) + 2;
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- else
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- return -EINVAL;
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+ ssb_extif_gpio_intmask(&bus->extif, BIT(gpio), 0);
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+}
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+
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+static void ssb_gpio_irq_extif_unmask(struct irq_data *d)
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+{
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+ struct ssb_bus *bus = irq_data_get_irq_chip_data(d);
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+ int gpio = irqd_to_hwirq(d);
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+ u32 val = ssb_extif_gpio_in(&bus->extif, BIT(gpio));
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+
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+ ssb_extif_gpio_polarity(&bus->extif, BIT(gpio), val);
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+ ssb_extif_gpio_intmask(&bus->extif, BIT(gpio), BIT(gpio));
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+}
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+
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+static struct irq_chip ssb_gpio_irq_extif_chip = {
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+ .name = "SSB-GPIO-EXTIF",
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+ .irq_mask = ssb_gpio_irq_extif_mask,
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+ .irq_unmask = ssb_gpio_irq_extif_unmask,
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+};
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+
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+static irqreturn_t ssb_gpio_irq_extif_handler(int irq, void *dev_id)
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+{
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+ struct ssb_bus *bus = dev_id;
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+ struct ssb_extif *extif = &bus->extif;
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+ u32 val = ssb_read32(extif->dev, SSB_EXTIF_GPIO_IN);
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+ u32 mask = ssb_read32(extif->dev, SSB_EXTIF_GPIO_INTMASK);
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+ u32 pol = ssb_read32(extif->dev, SSB_EXTIF_GPIO_INTPOL);
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+ unsigned long irqs = (val ^ pol) & mask;
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+ int gpio;
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+
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+ if (!irqs)
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+ return IRQ_NONE;
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+
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+ for_each_set_bit(gpio, &irqs, bus->gpio.ngpio)
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+ generic_handle_irq(ssb_gpio_to_irq(&bus->gpio, gpio));
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+ ssb_extif_gpio_polarity(extif, irqs, val & irqs);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static int ssb_gpio_irq_extif_domain_init(struct ssb_bus *bus)
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+{
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+ struct ssb_extif *extif = &bus->extif;
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+ struct gpio_chip *chip = &bus->gpio;
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+ int gpio, hwirq, err;
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+
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+ if (bus->bustype != SSB_BUSTYPE_SSB)
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+ return 0;
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+
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+ bus->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
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+ &irq_domain_simple_ops, extif);
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+ if (!bus->irq_domain) {
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+ err = -ENODEV;
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+ goto err_irq_domain;
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+ }
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+ for (gpio = 0; gpio < chip->ngpio; gpio++) {
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+ int irq = irq_create_mapping(bus->irq_domain, gpio);
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+
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+ irq_set_chip_data(irq, bus);
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+ irq_set_chip_and_handler(irq, &ssb_gpio_irq_extif_chip,
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+ handle_simple_irq);
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+ }
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+
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+ hwirq = ssb_mips_irq(bus->extif.dev) + 2;
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+ err = request_irq(hwirq, ssb_gpio_irq_extif_handler, IRQF_SHARED,
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+ "gpio", bus);
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+ if (err)
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+ goto err_req_irq;
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+
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+ ssb_extif_gpio_intmask(&bus->extif, ~0, 0);
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+
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+ return 0;
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+
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+err_req_irq:
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+ for (gpio = 0; gpio < chip->ngpio; gpio++) {
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+ int irq = irq_find_mapping(bus->irq_domain, gpio);
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+
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+ irq_dispose_mapping(irq);
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+ }
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+ irq_domain_remove(bus->irq_domain);
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+err_irq_domain:
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+ return err;
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}
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+static void ssb_gpio_irq_extif_domain_exit(struct ssb_bus *bus)
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+{
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+ struct ssb_extif *extif = &bus->extif;
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+ struct gpio_chip *chip = &bus->gpio;
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+ int gpio;
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+
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+ if (bus->bustype != SSB_BUSTYPE_SSB)
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+ return;
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+
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+ free_irq(ssb_mips_irq(bus->extif.dev) + 2, extif);
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+ for (gpio = 0; gpio < chip->ngpio; gpio++) {
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+ int irq = irq_find_mapping(bus->irq_domain, gpio);
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+
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+ irq_dispose_mapping(irq);
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+ }
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+ irq_domain_remove(bus->irq_domain);
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+}
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+#else
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+static int ssb_gpio_irq_extif_domain_init(struct ssb_bus *bus)
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+{
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+ return 0;
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+}
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+
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+static void ssb_gpio_irq_extif_domain_exit(struct ssb_bus *bus)
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+{
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+}
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+#endif
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+
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static int ssb_gpio_extif_init(struct ssb_bus *bus)
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{
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struct gpio_chip *chip = &bus->gpio;
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+ int err;
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chip->label = "ssb_extif_gpio";
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chip->owner = THIS_MODULE;
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@@ -165,7 +423,9 @@ static int ssb_gpio_extif_init(struct ss
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chip->set = ssb_gpio_extif_set_value;
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chip->direction_input = ssb_gpio_extif_direction_input;
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chip->direction_output = ssb_gpio_extif_direction_output;
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- chip->to_irq = ssb_gpio_extif_to_irq;
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+#if IS_ENABLED(CONFIG_SSB_EMBEDDED)
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+ chip->to_irq = ssb_gpio_to_irq;
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+#endif
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chip->ngpio = 5;
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/* There is just one SoC in one device and its GPIO addresses should be
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* deterministic to address them more easily. The other buses could get
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@@ -175,7 +435,17 @@ static int ssb_gpio_extif_init(struct ss
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else
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chip->base = -1;
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- return gpiochip_add(chip);
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+ err = ssb_gpio_irq_extif_domain_init(bus);
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+ if (err)
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+ return err;
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+
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+ err = gpiochip_add(chip);
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+ if (err) {
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+ ssb_gpio_irq_extif_domain_exit(bus);
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+ return err;
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+ }
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+
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+ return 0;
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}
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#else
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@@ -185,6 +455,10 @@ static int ssb_gpio_extif_init(struct ss
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}
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#endif
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+/**************************************************
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+ * Init
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+ **************************************************/
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+
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int ssb_gpio_init(struct ssb_bus *bus)
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{
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if (ssb_chipco_available(&bus->chipco))
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--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -593,6 +593,13 @@ static int ssb_attach_queued_buses(void)
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ssb_pcicore_init(&bus->pcicore);
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if (bus->bustype == SSB_BUSTYPE_SSB)
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ssb_watchdog_register(bus);
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+
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+ err = ssb_gpio_init(bus);
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+ if (err == -ENOTSUPP)
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+ ssb_dbg("GPIO driver not activated\n");
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+ else if (err)
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+ ssb_dbg("Error registering GPIO driver: %i\n", err);
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+
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ssb_bus_may_powerdown(bus);
|
|
|
|
err = ssb_devices_register(bus);
|
|
@@ -830,11 +837,6 @@ static int ssb_bus_register(struct ssb_b
|
|
ssb_chipcommon_init(&bus->chipco);
|
|
ssb_extif_init(&bus->extif);
|
|
ssb_mipscore_init(&bus->mipscore);
|
|
- err = ssb_gpio_init(bus);
|
|
- if (err == -ENOTSUPP)
|
|
- ssb_dbg("GPIO driver not activated\n");
|
|
- else if (err)
|
|
- ssb_dbg("Error registering GPIO driver: %i\n", err);
|
|
err = ssb_fetch_invariants(bus, get_invariants);
|
|
if (err) {
|
|
ssb_bus_may_powerdown(bus);
|
|
--- a/drivers/ssb/pci.c
|
|
+++ b/drivers/ssb/pci.c
|
|
@@ -326,13 +326,13 @@ err_ctlreg:
|
|
return err;
|
|
}
|
|
|
|
-static s8 r123_extract_antgain(u8 sprom_revision, const u16 *in,
|
|
- u16 mask, u16 shift)
|
|
+static s8 sprom_extract_antgain(u8 sprom_revision, const u16 *in, u16 offset,
|
|
+ u16 mask, u16 shift)
|
|
{
|
|
u16 v;
|
|
u8 gain;
|
|
|
|
- v = in[SPOFF(SSB_SPROM1_AGAIN)];
|
|
+ v = in[SPOFF(offset)];
|
|
gain = (v & mask) >> shift;
|
|
if (gain == 0xFF)
|
|
gain = 2; /* If unset use 2dBm */
|
|
@@ -416,12 +416,14 @@ static void sprom_extract_r123(struct ss
|
|
SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
|
|
|
|
/* Extract the antenna gain values. */
|
|
- out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
|
|
- SSB_SPROM1_AGAIN_BG,
|
|
- SSB_SPROM1_AGAIN_BG_SHIFT);
|
|
- out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
|
|
- SSB_SPROM1_AGAIN_A,
|
|
- SSB_SPROM1_AGAIN_A_SHIFT);
|
|
+ out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM1_AGAIN,
|
|
+ SSB_SPROM1_AGAIN_BG,
|
|
+ SSB_SPROM1_AGAIN_BG_SHIFT);
|
|
+ out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM1_AGAIN,
|
|
+ SSB_SPROM1_AGAIN_A,
|
|
+ SSB_SPROM1_AGAIN_A_SHIFT);
|
|
if (out->revision >= 2)
|
|
sprom_extract_r23(out, in);
|
|
}
|
|
@@ -468,7 +470,15 @@ static void sprom_extract_r458(struct ss
|
|
|
|
static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
|
|
{
|
|
+ static const u16 pwr_info_offset[] = {
|
|
+ SSB_SPROM4_PWR_INFO_CORE0, SSB_SPROM4_PWR_INFO_CORE1,
|
|
+ SSB_SPROM4_PWR_INFO_CORE2, SSB_SPROM4_PWR_INFO_CORE3
|
|
+ };
|
|
u16 il0mac_offset;
|
|
+ int i;
|
|
+
|
|
+ BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
|
|
+ ARRAY_SIZE(out->core_pwr_info));
|
|
|
|
if (out->revision == 4)
|
|
il0mac_offset = SSB_SPROM4_IL0MAC;
|
|
@@ -524,14 +534,59 @@ static void sprom_extract_r45(struct ssb
|
|
}
|
|
|
|
/* Extract the antenna gain values. */
|
|
- SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
|
|
- SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
|
|
- SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
|
|
- SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
|
|
- SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
|
|
- SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
|
|
- SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
|
|
- SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
|
|
+ out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM4_AGAIN01,
|
|
+ SSB_SPROM4_AGAIN0,
|
|
+ SSB_SPROM4_AGAIN0_SHIFT);
|
|
+ out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM4_AGAIN01,
|
|
+ SSB_SPROM4_AGAIN1,
|
|
+ SSB_SPROM4_AGAIN1_SHIFT);
|
|
+ out->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM4_AGAIN23,
|
|
+ SSB_SPROM4_AGAIN2,
|
|
+ SSB_SPROM4_AGAIN2_SHIFT);
|
|
+ out->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM4_AGAIN23,
|
|
+ SSB_SPROM4_AGAIN3,
|
|
+ SSB_SPROM4_AGAIN3_SHIFT);
|
|
+
|
|
+ /* Extract cores power info info */
|
|
+ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
|
|
+ u16 o = pwr_info_offset[i];
|
|
+
|
|
+ SPEX(core_pwr_info[i].itssi_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,
|
|
+ SSB_SPROM4_2G_ITSSI, SSB_SPROM4_2G_ITSSI_SHIFT);
|
|
+ SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,
|
|
+ SSB_SPROM4_2G_MAXP, 0);
|
|
+
|
|
+ SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SPROM4_2G_PA_0, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SPROM4_2G_PA_1, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SPROM4_2G_PA_2, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_2g[3], o + SSB_SPROM4_2G_PA_3, ~0, 0);
|
|
+
|
|
+ SPEX(core_pwr_info[i].itssi_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,
|
|
+ SSB_SPROM4_5G_ITSSI, SSB_SPROM4_5G_ITSSI_SHIFT);
|
|
+ SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,
|
|
+ SSB_SPROM4_5G_MAXP, 0);
|
|
+ SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM4_5GHL_MAXP,
|
|
+ SSB_SPROM4_5GH_MAXP, 0);
|
|
+ SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM4_5GHL_MAXP,
|
|
+ SSB_SPROM4_5GL_MAXP, SSB_SPROM4_5GL_MAXP_SHIFT);
|
|
+
|
|
+ SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SPROM4_5GL_PA_0, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SPROM4_5GL_PA_1, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SPROM4_5GL_PA_2, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gl[3], o + SSB_SPROM4_5GL_PA_3, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SPROM4_5G_PA_0, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SPROM4_5G_PA_1, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SPROM4_5G_PA_2, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5g[3], o + SSB_SPROM4_5G_PA_3, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SPROM4_5GH_PA_0, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SPROM4_5GH_PA_1, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SPROM4_5GH_PA_2, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gh[3], o + SSB_SPROM4_5GH_PA_3, ~0, 0);
|
|
+ }
|
|
|
|
sprom_extract_r458(out, in);
|
|
|
|
@@ -621,14 +676,22 @@ static void sprom_extract_r8(struct ssb_
|
|
SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
|
|
|
|
/* Extract the antenna gain values. */
|
|
- SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
|
|
- SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
|
|
- SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
|
|
- SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
|
|
- SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
|
|
- SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
|
|
- SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
|
|
- SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
|
|
+ out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM8_AGAIN01,
|
|
+ SSB_SPROM8_AGAIN0,
|
|
+ SSB_SPROM8_AGAIN0_SHIFT);
|
|
+ out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM8_AGAIN01,
|
|
+ SSB_SPROM8_AGAIN1,
|
|
+ SSB_SPROM8_AGAIN1_SHIFT);
|
|
+ out->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM8_AGAIN23,
|
|
+ SSB_SPROM8_AGAIN2,
|
|
+ SSB_SPROM8_AGAIN2_SHIFT);
|
|
+ out->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM8_AGAIN23,
|
|
+ SSB_SPROM8_AGAIN3,
|
|
+ SSB_SPROM8_AGAIN3_SHIFT);
|
|
|
|
/* Extract cores power info info */
|
|
for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
|
|
--- a/include/linux/ssb/ssb.h
|
|
+++ b/include/linux/ssb/ssb.h
|
|
@@ -33,6 +33,7 @@ struct ssb_sprom {
|
|
u8 et1phyaddr; /* MII address for enet1 */
|
|
u8 et0mdcport; /* MDIO for enet0 */
|
|
u8 et1mdcport; /* MDIO for enet1 */
|
|
+ u16 dev_id; /* Device ID overriding e.g. PCI ID */
|
|
u16 board_rev; /* Board revision number from SPROM. */
|
|
u16 board_num; /* Board number from SPROM. */
|
|
u16 board_type; /* Board type from SPROM. */
|
|
@@ -486,6 +487,7 @@ struct ssb_bus {
|
|
#endif /* EMBEDDED */
|
|
#ifdef CONFIG_SSB_DRIVER_GPIO
|
|
struct gpio_chip gpio;
|
|
+ struct irq_domain *irq_domain;
|
|
#endif /* DRIVER_GPIO */
|
|
|
|
/* Internal-only stuff follows. Do not touch. */
|
|
--- a/include/linux/ssb/ssb_regs.h
|
|
+++ b/include/linux/ssb/ssb_regs.h
|
|
@@ -345,6 +345,43 @@
|
|
#define SSB_SPROM4_TXPID5GH2_SHIFT 0
|
|
#define SSB_SPROM4_TXPID5GH3 0xFF00
|
|
#define SSB_SPROM4_TXPID5GH3_SHIFT 8
|
|
+
|
|
+/* There are 4 blocks with power info sharing the same layout */
|
|
+#define SSB_SPROM4_PWR_INFO_CORE0 0x0080
|
|
+#define SSB_SPROM4_PWR_INFO_CORE1 0x00AE
|
|
+#define SSB_SPROM4_PWR_INFO_CORE2 0x00DC
|
|
+#define SSB_SPROM4_PWR_INFO_CORE3 0x010A
|
|
+
|
|
+#define SSB_SPROM4_2G_MAXP_ITSSI 0x00 /* 2 GHz ITSSI and 2 GHz Max Power */
|
|
+#define SSB_SPROM4_2G_MAXP 0x00FF
|
|
+#define SSB_SPROM4_2G_ITSSI 0xFF00
|
|
+#define SSB_SPROM4_2G_ITSSI_SHIFT 8
|
|
+#define SSB_SPROM4_2G_PA_0 0x02 /* 2 GHz power amp */
|
|
+#define SSB_SPROM4_2G_PA_1 0x04
|
|
+#define SSB_SPROM4_2G_PA_2 0x06
|
|
+#define SSB_SPROM4_2G_PA_3 0x08
|
|
+#define SSB_SPROM4_5G_MAXP_ITSSI 0x0A /* 5 GHz ITSSI and 5.3 GHz Max Power */
|
|
+#define SSB_SPROM4_5G_MAXP 0x00FF
|
|
+#define SSB_SPROM4_5G_ITSSI 0xFF00
|
|
+#define SSB_SPROM4_5G_ITSSI_SHIFT 8
|
|
+#define SSB_SPROM4_5GHL_MAXP 0x0C /* 5.2 GHz and 5.8 GHz Max Power */
|
|
+#define SSB_SPROM4_5GH_MAXP 0x00FF
|
|
+#define SSB_SPROM4_5GL_MAXP 0xFF00
|
|
+#define SSB_SPROM4_5GL_MAXP_SHIFT 8
|
|
+#define SSB_SPROM4_5G_PA_0 0x0E /* 5.3 GHz power amp */
|
|
+#define SSB_SPROM4_5G_PA_1 0x10
|
|
+#define SSB_SPROM4_5G_PA_2 0x12
|
|
+#define SSB_SPROM4_5G_PA_3 0x14
|
|
+#define SSB_SPROM4_5GL_PA_0 0x16 /* 5.2 GHz power amp */
|
|
+#define SSB_SPROM4_5GL_PA_1 0x18
|
|
+#define SSB_SPROM4_5GL_PA_2 0x1A
|
|
+#define SSB_SPROM4_5GL_PA_3 0x1C
|
|
+#define SSB_SPROM4_5GH_PA_0 0x1E /* 5.8 GHz power amp */
|
|
+#define SSB_SPROM4_5GH_PA_1 0x20
|
|
+#define SSB_SPROM4_5GH_PA_2 0x22
|
|
+#define SSB_SPROM4_5GH_PA_3 0x24
|
|
+
|
|
+/* TODO: Make it deprecated */
|
|
#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
|
|
#define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
|
|
#define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
|
|
--- a/arch/mips/bcm47xx/sprom.c
|
|
+++ b/arch/mips/bcm47xx/sprom.c
|
|
@@ -168,6 +168,7 @@ static void nvram_read_alpha2(const char
|
|
static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom,
|
|
const char *prefix, bool fallback)
|
|
{
|
|
+ nvram_read_u16(prefix, NULL, "devid", &sprom->dev_id, 0, fallback);
|
|
nvram_read_u8(prefix, NULL, "ledbh0", &sprom->gpio0, 0xff, fallback);
|
|
nvram_read_u8(prefix, NULL, "ledbh1", &sprom->gpio1, 0xff, fallback);
|
|
nvram_read_u8(prefix, NULL, "ledbh2", &sprom->gpio2, 0xff, fallback);
|