mirror of https://github.com/hak5/openwrt-owl.git
186 lines
5.2 KiB
Diff
186 lines
5.2 KiB
Diff
From fc5783a00be9251196091be6b9cdd54fe196630b Mon Sep 17 00:00:00 2001
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From: Marko Ratkaj <marko.ratkaj@sartura.hr>
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Date: Fri, 7 Apr 2017 11:24:19 +0200
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Subject: [PATCH] armada-38x-solidrun-microsom backport improvements from
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upstream
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Signed-off-by: Marko Ratkaj <marko.ratkaj@sartura.hr>
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---
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.../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 130 ++++++++++++---------
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1 file changed, 74 insertions(+), 56 deletions(-)
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--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
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+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
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@@ -17,17 +17,17 @@
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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- * This file is distributed in the hope that it will be useful
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+ * This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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- * Or, alternatively
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+ * Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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- * restriction, including without limitation the rights to use
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+ * restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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@@ -36,11 +36,11 @@
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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@@ -62,45 +62,6 @@
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MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
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internal-regs {
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- ethernet@70000 {
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- pinctrl-0 = <&ge0_rgmii_pins>;
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- pinctrl-names = "default";
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- phy = <&phy_dedicated>;
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- phy-mode = "rgmii-id";
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- buffer-manager = <&bm>;
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- bm,pool-long = <0>;
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- bm,pool-short = <1>;
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- status = "okay";
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- };
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-
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- mdio@72004 {
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- /*
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- * Add the phy clock here, so the phy can be
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- * accessed to read its IDs prior to binding
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- * with the driver.
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- */
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- pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>;
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- pinctrl-names = "default";
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-
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- phy_dedicated: ethernet-phy@0 {
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- /*
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- * Annoyingly, the marvell phy driver
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- * configures the LED register, rather
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- * than preserving reset-loaded setting.
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- * We undo that rubbish here.
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- */
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- marvell,reg-init = <3 16 0 0x101e>;
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- reg = <0>;
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- };
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- };
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-
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- pinctrl@18000 {
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- microsom_phy_clk_pins: microsom-phy-clk-pins {
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- marvell,pins = "mpp45";
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- marvell,function = "ref";
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- };
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- };
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-
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rtc@a3800 {
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/*
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* If the rtc doesn't work, run "date reset"
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@@ -108,21 +69,78 @@
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*/
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status = "okay";
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};
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+ };
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+ };
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+};
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- serial@12000 {
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- pinctrl-0 = <&uart0_pins>;
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- pinctrl-names = "default";
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- status = "okay";
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- };
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+&bm {
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+ status = "okay";
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+};
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- bm@c8000 {
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- status = "okay";
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- };
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- };
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+&bm_bppi {
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+ status = "okay";
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+};
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- bm-bppi {
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- status = "okay";
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- };
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+ð0 {
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+ /* ethernet@70000 */
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+ pinctrl-0 = <&ge0_rgmii_pins>;
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+ pinctrl-names = "default";
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+ phy = <&phy_dedicated>;
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+ phy-mode = "rgmii-id";
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+ buffer-manager = <&bm>;
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+ bm,pool-long = <0>;
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+ bm,pool-short = <1>;
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+ status = "okay";
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+};
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+&mdio {
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+ /*
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+ * Add the phy clock here, so the phy can be accessed to read its
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+ * IDs prior to binding with the driver.
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+ */
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+ pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>;
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+ pinctrl-names = "default";
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+
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+ phy_dedicated: ethernet-phy@0 {
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+ /*
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+ * Annoyingly, the marvell phy driver configures the LED
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+ * register, rather than preserving reset-loaded setting.
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+ * We undo that rubbish here.
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+ */
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+ marvell,reg-init = <3 16 0 0x101e>;
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+ reg = <0>;
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};
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};
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+
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+&pinctrl {
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+ microsom_phy_clk_pins: microsom-phy-clk-pins {
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+ marvell,pins = "mpp45";
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+ marvell,function = "ref";
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+ };
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+ /* Optional eMMC */
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+ microsom_sdhci_pins: microsom-sdhci-pins {
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+ marvell,pins = "mpp21", "mpp28", "mpp37",
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+ "mpp38", "mpp39", "mpp40";
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+ marvell,function = "sd0";
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+ };
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+};
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+
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+&spi1 {
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+ /* The microsom has an optional W25Q32 on board, connected to CS0 */
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+ pinctrl-0 = <&spi1_pins>;
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+
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+ w25q32: spi-flash@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "w25q32", "jedec,spi-nor";
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+ reg = <0>; /* Chip select 0 */
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+ spi-max-frequency = <3000000>;
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+ status = "disabled";
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+ };
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+};
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+
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+&uart0 {
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+ pinctrl-0 = <&uart0_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+};
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