mirror of https://github.com/hak5/openwrt-owl.git
79 lines
2.7 KiB
Diff
79 lines
2.7 KiB
Diff
From 948603d4d637a0e04a3214253b911cfc4ed11220 Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Mon, 21 Mar 2016 14:44:35 +0100
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Subject: [PATCH] sunxi: Fix 2nd usb controller on sun4i/sun7i no longer
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working
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The 2nd usb controller on sun4i/sun7i has its base address 0x8000
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bytes from the 1st one, rather then 0x1000. Also the ahb clk gates
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are interleaved with the ohci clk-gates introducing a hole between
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the clks for usb1 and usb2.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Acked-by: Ian Campbell <ijc@hellion.org.uk>
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---
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drivers/usb/host/ehci-sunxi.c | 13 +++++++++++--
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drivers/usb/host/ohci-sunxi.c | 15 ++++++++++++---
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2 files changed, 23 insertions(+), 5 deletions(-)
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--- a/drivers/usb/host/ehci-sunxi.c
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+++ b/drivers/usb/host/ehci-sunxi.c
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@@ -17,6 +17,14 @@
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#include <dm.h>
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#include "ehci.h"
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+#ifdef CONFIG_SUNXI_GEN_SUN4I
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+#define BASE_DIST 0x8000
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+#define AHB_CLK_DIST 2
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+#else
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+#define BASE_DIST 0x1000
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+#define AHB_CLK_DIST 1
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+#endif
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+
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struct ehci_sunxi_priv {
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struct ehci_ctrl ehci;
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int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
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@@ -39,8 +47,9 @@ static int ehci_usb_probe(struct udevice
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#ifdef CONFIG_MACH_SUN8I_H3
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priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0;
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#endif
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- priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1;
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- priv->ahb_gate_mask <<= priv->phy_index - 1;
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+ priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / BASE_DIST;
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+ priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
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+ priv->phy_index++; /* Non otg phys start at 1 */
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setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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--- a/drivers/usb/host/ohci-sunxi.c
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+++ b/drivers/usb/host/ohci-sunxi.c
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@@ -17,6 +17,14 @@
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#include <usb.h>
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#include "ohci.h"
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+#ifdef CONFIG_SUNXI_GEN_SUN4I
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+#define BASE_DIST 0x8000
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+#define AHB_CLK_DIST 2
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+#else
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+#define BASE_DIST 0x1000
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+#define AHB_CLK_DIST 1
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+#endif
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+
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struct ohci_sunxi_priv {
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ohci_t ohci;
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int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
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@@ -42,9 +50,10 @@ static int ohci_usb_probe(struct udevice
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priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0;
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#endif
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priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
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- priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1;
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- priv->ahb_gate_mask <<= priv->phy_index - 1;
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- priv->usb_gate_mask <<= priv->phy_index - 1;
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+ priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
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+ priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
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+ priv->usb_gate_mask <<= priv->phy_index;
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+ priv->phy_index++; /* Non otg phys start at 1 */
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setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
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setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);
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