mirror of https://github.com/hak5/openwrt-owl.git
3017 lines
92 KiB
Diff
3017 lines
92 KiB
Diff
--- a/arch/mips/bcm47xx/serial.c
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+++ b/arch/mips/bcm47xx/serial.c
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@@ -62,7 +62,7 @@ static int __init uart8250_init_bcma(voi
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p->mapbase = (unsigned int) bcma_port->regs;
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p->membase = (void *) bcma_port->regs;
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- p->irq = bcma_port->irq + 2;
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+ p->irq = bcma_port->irq;
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p->uartclk = bcma_port->baud_base;
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p->regshift = bcma_port->reg_shift;
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p->iotype = UPIO_MEM;
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--- a/drivers/bcma/Kconfig
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+++ b/drivers/bcma/Kconfig
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@@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
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config BCMA_HOST_PCI
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bool "Support for BCMA on PCI-host bus"
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depends on BCMA_HOST_PCI_POSSIBLE
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+ default y
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config BCMA_DRIVER_PCI_HOSTMODE
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bool "Driver for PCI core working in hostmode"
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@@ -48,12 +49,12 @@ config BCMA_DRIVER_MIPS
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config BCMA_SFLASH
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bool
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- depends on BCMA_DRIVER_MIPS && BROKEN
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+ depends on BCMA_DRIVER_MIPS
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default y
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config BCMA_NFLASH
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bool
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- depends on BCMA_DRIVER_MIPS && BROKEN
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+ depends on BCMA_DRIVER_MIPS
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default y
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config BCMA_DRIVER_GMAC_CMN
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@@ -65,6 +66,14 @@ config BCMA_DRIVER_GMAC_CMN
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If unsure, say N
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+config BCMA_DRIVER_GPIO
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+ bool "BCMA GPIO driver"
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+ depends on BCMA && GPIOLIB
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+ help
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+ Driver to provide access to the GPIO pins of the bcma bus.
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+
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+ If unsure, say N
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+
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config BCMA_DEBUG
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bool "BCMA debugging"
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depends on BCMA
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--- a/drivers/bcma/Makefile
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+++ b/drivers/bcma/Makefile
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@@ -6,6 +6,7 @@ bcma-y += driver_pci.o
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bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
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bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
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bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
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+bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
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bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
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bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
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obj-$(CONFIG_BCMA) += bcma.o
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--- a/drivers/bcma/bcma_private.h
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+++ b/drivers/bcma/bcma_private.h
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@@ -22,6 +22,8 @@
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struct bcma_bus;
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/* main.c */
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+bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
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+ int timeout);
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int __devinit bcma_bus_register(struct bcma_bus *bus);
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void bcma_bus_unregister(struct bcma_bus *bus);
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int __init bcma_bus_early_register(struct bcma_bus *bus,
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@@ -31,6 +33,8 @@ int __init bcma_bus_early_register(struc
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int bcma_bus_suspend(struct bcma_bus *bus);
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int bcma_bus_resume(struct bcma_bus *bus);
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#endif
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+struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
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+ u8 unit);
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/* scan.c */
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int bcma_bus_scan(struct bcma_bus *bus);
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@@ -45,15 +49,17 @@ int bcma_sprom_get(struct bcma_bus *bus)
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/* driver_chipcommon.c */
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#ifdef CONFIG_BCMA_DRIVER_MIPS
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void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
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+extern struct platform_device bcma_pflash_dev;
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#endif /* CONFIG_BCMA_DRIVER_MIPS */
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/* driver_chipcommon_pmu.c */
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-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
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-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
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+u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
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+u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
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#ifdef CONFIG_BCMA_SFLASH
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/* driver_chipcommon_sflash.c */
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int bcma_sflash_init(struct bcma_drv_cc *cc);
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+extern struct platform_device bcma_sflash_dev;
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#else
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static inline int bcma_sflash_init(struct bcma_drv_cc *cc)
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{
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@@ -65,6 +71,7 @@ static inline int bcma_sflash_init(struc
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#ifdef CONFIG_BCMA_NFLASH
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/* driver_chipcommon_nflash.c */
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int bcma_nflash_init(struct bcma_drv_cc *cc);
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+extern struct platform_device bcma_nflash_dev;
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#else
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static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
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{
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@@ -82,9 +89,26 @@ extern void __exit bcma_host_pci_exit(vo
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/* driver_pci.c */
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u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
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+extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
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+
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#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
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bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
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void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
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#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
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+#ifdef CONFIG_BCMA_DRIVER_GPIO
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+/* driver_gpio.c */
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+int bcma_gpio_init(struct bcma_drv_cc *cc);
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+int bcma_gpio_unregister(struct bcma_drv_cc *cc);
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+#else
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+static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
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+{
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+ return -ENOTSUPP;
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+}
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+static inline int bcma_gpio_unregister(struct bcma_drv_cc *cc)
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+{
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+ return 0;
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+}
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+#endif /* CONFIG_BCMA_DRIVER_GPIO */
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+
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#endif
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--- a/drivers/bcma/core.c
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+++ b/drivers/bcma/core.c
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@@ -9,6 +9,25 @@
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#include <linux/export.h>
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#include <linux/bcma/bcma.h>
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+static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
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+ u32 value, int timeout)
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+{
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+ unsigned long deadline = jiffies + timeout;
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+ u32 val;
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+
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+ do {
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+ val = bcma_aread32(core, reg);
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+ if ((val & mask) == value)
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+ return true;
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+ cpu_relax();
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+ udelay(10);
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+ } while (!time_after_eq(jiffies, deadline));
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+
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+ bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
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+
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+ return false;
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+}
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+
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bool bcma_core_is_enabled(struct bcma_device *core)
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{
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if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
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@@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
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if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
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return;
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- bcma_awrite32(core, BCMA_IOCTL, flags);
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- bcma_aread32(core, BCMA_IOCTL);
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- udelay(10);
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+ bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
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bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
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bcma_aread32(core, BCMA_RESET_CTL);
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udelay(1);
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+
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+ bcma_awrite32(core, BCMA_IOCTL, flags);
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+ bcma_aread32(core, BCMA_IOCTL);
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+ udelay(10);
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}
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EXPORT_SYMBOL_GPL(bcma_core_disable);
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@@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
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bcma_aread32(core, BCMA_IOCTL);
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bcma_awrite32(core, BCMA_RESET_CTL, 0);
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+ bcma_aread32(core, BCMA_RESET_CTL);
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udelay(1);
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bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
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@@ -65,7 +87,7 @@ void bcma_core_set_clockmode(struct bcma
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switch (clkmode) {
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case BCMA_CLKMODE_FAST:
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bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
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- udelay(64);
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+ usleep_range(64, 300);
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for (i = 0; i < 1500; i++) {
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if (bcma_read32(core, BCMA_CLKCTLST) &
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BCMA_CLKCTLST_HAVEHT) {
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@@ -104,7 +126,13 @@ void bcma_core_pll_ctl(struct bcma_devic
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if (i)
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bcma_err(core->bus, "PLL enable timeout\n");
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} else {
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- bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
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+ /*
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+ * Mask the PLL but don't wait for it to be disabled. PLL may be
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+ * shared between cores and will be still up if there is another
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+ * core using it.
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+ */
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+ bcma_mask32(core, BCMA_CLKCTLST, ~req);
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+ bcma_read32(core, BCMA_CLKCTLST);
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}
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}
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EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
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--- a/drivers/bcma/driver_chipcommon.c
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+++ b/drivers/bcma/driver_chipcommon.c
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@@ -4,12 +4,15 @@
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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+#include <linux/bcm47xx_wdt.h>
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#include <linux/export.h>
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+#include <linux/platform_device.h>
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#include <linux/bcma/bcma.h>
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static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
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@@ -22,23 +25,130 @@ static inline u32 bcma_cc_write32_masked
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return value;
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}
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-void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
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+u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
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{
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- u32 leddc_on = 10;
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- u32 leddc_off = 90;
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+ if (cc->capabilities & BCMA_CC_CAP_PMU)
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+ return bcma_pmu_get_alp_clock(cc);
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- if (cc->setup_done)
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+ return 20000000;
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+}
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+EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
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+
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+static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
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+{
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+ struct bcma_bus *bus = cc->core->bus;
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+ u32 nb;
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+
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+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
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+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
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+ nb = 32;
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+ else if (cc->core->id.rev < 26)
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+ nb = 16;
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+ else
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+ nb = (cc->core->id.rev >= 37) ? 32 : 24;
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+ } else {
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+ nb = 28;
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+ }
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+ if (nb == 32)
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+ return 0xffffffff;
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+ else
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+ return (1 << nb) - 1;
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+}
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+
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+static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
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+ u32 ticks)
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+{
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+ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
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+
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+ return bcma_chipco_watchdog_timer_set(cc, ticks);
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+}
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+
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+static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
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+ u32 ms)
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+{
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+ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
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+ u32 ticks;
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+
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+ ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
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+ return ticks / cc->ticks_per_ms;
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+}
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+
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+static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
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+{
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+ struct bcma_bus *bus = cc->core->bus;
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+
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+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
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+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
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+ /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
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+ return bcma_chipco_get_alp_clock(cc) / 4000;
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+ else
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+ /* based on 32KHz ILP clock */
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+ return 32;
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+ } else {
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+ return bcma_chipco_get_alp_clock(cc) / 1000;
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+ }
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+}
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+
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+int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
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+{
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+ struct bcm47xx_wdt wdt = {};
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+ struct platform_device *pdev;
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+
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+ wdt.driver_data = cc;
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+ wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
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+ wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
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+ wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
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+
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+ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
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+ cc->core->bus->num, &wdt,
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+ sizeof(wdt));
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+ if (IS_ERR(pdev))
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+ return PTR_ERR(pdev);
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+
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+ cc->watchdog = pdev;
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+
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+ return 0;
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+}
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+
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+void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
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+{
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+ if (cc->early_setup_done)
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return;
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+ spin_lock_init(&cc->gpio_lock);
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+
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if (cc->core->id.rev >= 11)
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cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
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cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
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if (cc->core->id.rev >= 35)
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cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
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+ if (cc->capabilities & BCMA_CC_CAP_PMU)
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+ bcma_pmu_early_init(cc);
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+
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+ cc->early_setup_done = true;
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+}
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+
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+void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
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+{
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+ u32 leddc_on = 10;
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+ u32 leddc_off = 90;
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+
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+ if (cc->setup_done)
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+ return;
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+
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+ bcma_core_chipcommon_early_init(cc);
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+
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if (cc->core->id.rev >= 20) {
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- bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
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- bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
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+ u32 pullup = 0, pulldown = 0;
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+
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+ if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
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+ pullup = 0x402e0;
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+ pulldown = 0x20500;
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+ }
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+
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+ bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
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+ bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
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}
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if (cc->capabilities & BCMA_CC_CAP_PMU)
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@@ -56,15 +166,33 @@ void bcma_core_chipcommon_init(struct bc
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((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
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(leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
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}
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+ cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
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cc->setup_done = true;
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}
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/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
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-void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
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+u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
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{
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- /* instant NMI */
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- bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
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+ u32 maxt;
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+ enum bcma_clkmode clkmode;
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+
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+ maxt = bcma_chipco_watchdog_get_max_timer(cc);
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+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
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+ if (ticks == 1)
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+ ticks = 2;
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+ else if (ticks > maxt)
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+ ticks = maxt;
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+ bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
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+ } else {
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+ clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
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+ bcma_core_set_clockmode(cc->core, clkmode);
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+ if (ticks > maxt)
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+ ticks = maxt;
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+ /* instant NMI */
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+ bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
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+ }
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+ return ticks;
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}
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void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
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@@ -84,28 +212,99 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
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u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
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+ unsigned long flags;
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+ u32 res;
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+
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+ spin_lock_irqsave(&cc->gpio_lock, flags);
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+ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
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+ spin_unlock_irqrestore(&cc->gpio_lock, flags);
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+
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+ return res;
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}
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+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
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u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
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+ unsigned long flags;
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+ u32 res;
|
|
+
|
|
+ spin_lock_irqsave(&cc->gpio_lock, flags);
|
|
+ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
|
|
+ spin_unlock_irqrestore(&cc->gpio_lock, flags);
|
|
+
|
|
+ return res;
|
|
}
|
|
+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
|
|
|
|
+/*
|
|
+ * If the bit is set to 0, chipcommon controlls this GPIO,
|
|
+ * if the bit is set to 1, it is used by some part of the chip and not our code.
|
|
+ */
|
|
u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
|
{
|
|
- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
|
|
+ unsigned long flags;
|
|
+ u32 res;
|
|
+
|
|
+ spin_lock_irqsave(&cc->gpio_lock, flags);
|
|
+ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
|
|
+ spin_unlock_irqrestore(&cc->gpio_lock, flags);
|
|
+
|
|
+ return res;
|
|
}
|
|
EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
|
|
|
|
u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
|
{
|
|
- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
|
|
+ unsigned long flags;
|
|
+ u32 res;
|
|
+
|
|
+ spin_lock_irqsave(&cc->gpio_lock, flags);
|
|
+ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
|
|
+ spin_unlock_irqrestore(&cc->gpio_lock, flags);
|
|
+
|
|
+ return res;
|
|
}
|
|
|
|
u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
|
{
|
|
- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
|
|
+ unsigned long flags;
|
|
+ u32 res;
|
|
+
|
|
+ spin_lock_irqsave(&cc->gpio_lock, flags);
|
|
+ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
|
|
+ spin_unlock_irqrestore(&cc->gpio_lock, flags);
|
|
+
|
|
+ return res;
|
|
+}
|
|
+
|
|
+u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
|
+{
|
|
+ unsigned long flags;
|
|
+ u32 res;
|
|
+
|
|
+ if (cc->core->id.rev < 20)
|
|
+ return 0;
|
|
+
|
|
+ spin_lock_irqsave(&cc->gpio_lock, flags);
|
|
+ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
|
|
+ spin_unlock_irqrestore(&cc->gpio_lock, flags);
|
|
+
|
|
+ return res;
|
|
+}
|
|
+
|
|
+u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
|
+{
|
|
+ unsigned long flags;
|
|
+ u32 res;
|
|
+
|
|
+ if (cc->core->id.rev < 20)
|
|
+ return 0;
|
|
+
|
|
+ spin_lock_irqsave(&cc->gpio_lock, flags);
|
|
+ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
|
|
+ spin_unlock_irqrestore(&cc->gpio_lock, flags);
|
|
+
|
|
+ return res;
|
|
}
|
|
|
|
#ifdef CONFIG_BCMA_DRIVER_MIPS
|
|
@@ -118,8 +317,7 @@ void bcma_chipco_serial_init(struct bcma
|
|
struct bcma_serial_port *ports = cc->serial_ports;
|
|
|
|
if (ccrev >= 11 && ccrev != 15) {
|
|
- /* Fixed ALP clock */
|
|
- baud_base = bcma_pmu_alp_clock(cc);
|
|
+ baud_base = bcma_chipco_get_alp_clock(cc);
|
|
if (ccrev >= 21) {
|
|
/* Turn off UART clock before switching clocksource. */
|
|
bcma_cc_write32(cc, BCMA_CC_CORECTL,
|
|
@@ -141,7 +339,7 @@ void bcma_chipco_serial_init(struct bcma
|
|
return;
|
|
}
|
|
|
|
- irq = bcma_core_mips_irq(cc->core);
|
|
+ irq = bcma_core_irq(cc->core);
|
|
|
|
/* Determine the registers of the UARTs */
|
|
cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
|
|
--- a/drivers/bcma/driver_chipcommon_nflash.c
|
|
+++ b/drivers/bcma/driver_chipcommon_nflash.c
|
|
@@ -5,15 +5,40 @@
|
|
* Licensed under the GNU/GPL. See COPYING for details.
|
|
*/
|
|
|
|
+#include "bcma_private.h"
|
|
+
|
|
+#include <linux/platform_device.h>
|
|
#include <linux/bcma/bcma.h>
|
|
-#include <linux/bcma/bcma_driver_chipcommon.h>
|
|
-#include <linux/delay.h>
|
|
|
|
-#include "bcma_private.h"
|
|
+struct platform_device bcma_nflash_dev = {
|
|
+ .name = "bcma_nflash",
|
|
+ .num_resources = 0,
|
|
+};
|
|
|
|
/* Initialize NAND flash access */
|
|
int bcma_nflash_init(struct bcma_drv_cc *cc)
|
|
{
|
|
- bcma_err(cc->core->bus, "NAND flash support is broken\n");
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+
|
|
+ if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
|
|
+ cc->core->id.rev != 38) {
|
|
+ bcma_err(bus, "NAND flash on unsupported board!\n");
|
|
+ return -ENOTSUPP;
|
|
+ }
|
|
+
|
|
+ if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) {
|
|
+ bcma_err(bus, "NAND flash not present according to ChipCommon\n");
|
|
+ return -ENODEV;
|
|
+ }
|
|
+
|
|
+ cc->nflash.present = true;
|
|
+ if (cc->core->id.rev == 38 &&
|
|
+ (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
|
|
+ cc->nflash.boot = true;
|
|
+
|
|
+ /* Prepare platform device, but don't register it yet. It's too early,
|
|
+ * malloc (required by device_private_init) is not available yet. */
|
|
+ bcma_nflash_dev.dev.platform_data = &cc->nflash;
|
|
+
|
|
return 0;
|
|
}
|
|
--- a/drivers/bcma/driver_chipcommon_pmu.c
|
|
+++ b/drivers/bcma/driver_chipcommon_pmu.c
|
|
@@ -13,12 +13,13 @@
|
|
#include <linux/export.h>
|
|
#include <linux/bcma/bcma.h>
|
|
|
|
-static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
|
|
+u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
|
|
{
|
|
bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
|
|
bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
|
|
return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
|
|
}
|
|
+EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
|
|
|
|
void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
|
|
{
|
|
@@ -55,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
|
|
}
|
|
EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
|
|
|
|
+static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ u32 ilp_ctl, alp_hz;
|
|
+
|
|
+ if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
|
|
+ BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
|
|
+ return 0;
|
|
+
|
|
+ bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
|
|
+ BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
|
|
+ usleep_range(1000, 2000);
|
|
+
|
|
+ ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
|
|
+ ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
|
|
+
|
|
+ bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
|
|
+
|
|
+ alp_hz = ilp_ctl * 32768 / 4;
|
|
+ return (alp_hz + 50000) / 100000 * 100;
|
|
+}
|
|
+
|
|
+static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
|
|
+{
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+ u32 freq_tgt_target = 0, freq_tgt_current;
|
|
+ u32 pll0, mask;
|
|
+
|
|
+ switch (bus->chipinfo.id) {
|
|
+ case BCMA_CHIP_ID_BCM43142:
|
|
+ /* pmu2_xtaltab0_adfll_485 */
|
|
+ switch (xtalfreq) {
|
|
+ case 12000:
|
|
+ freq_tgt_target = 0x50D52;
|
|
+ break;
|
|
+ case 20000:
|
|
+ freq_tgt_target = 0x307FE;
|
|
+ break;
|
|
+ case 26000:
|
|
+ freq_tgt_target = 0x254EA;
|
|
+ break;
|
|
+ case 37400:
|
|
+ freq_tgt_target = 0x19EF8;
|
|
+ break;
|
|
+ case 52000:
|
|
+ freq_tgt_target = 0x12A75;
|
|
+ break;
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ if (!freq_tgt_target) {
|
|
+ bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
|
|
+ xtalfreq);
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
|
|
+ freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
|
|
+ BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
|
|
+
|
|
+ if (freq_tgt_current == freq_tgt_target) {
|
|
+ bcma_debug(bus, "Target TGT frequency already set\n");
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ /* Turn off PLL */
|
|
+ switch (bus->chipinfo.id) {
|
|
+ case BCMA_CHIP_ID_BCM43142:
|
|
+ mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
|
|
+ BCMA_RES_4314_MACPHY_CLK_AVAIL);
|
|
+
|
|
+ bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
|
|
+ bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
|
|
+ bcma_wait_value(cc->core, BCMA_CLKCTLST,
|
|
+ BCMA_CLKCTLST_HAVEHT, 0, 20000);
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
|
|
+ pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
|
|
+ bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
|
|
+
|
|
+ /* Flush */
|
|
+ if (cc->pmu.rev >= 2)
|
|
+ bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
|
|
+
|
|
+ /* TODO: Do we need to update OTP? */
|
|
+}
|
|
+
|
|
+static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+ u32 xtalfreq = bcma_pmu_xtalfreq(cc);
|
|
+
|
|
+ switch (bus->chipinfo.id) {
|
|
+ case BCMA_CHIP_ID_BCM43142:
|
|
+ if (xtalfreq == 0)
|
|
+ xtalfreq = 20000;
|
|
+ bcma_pmu2_pll_init0(cc, xtalfreq);
|
|
+ break;
|
|
+ }
|
|
+}
|
|
+
|
|
static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
|
|
{
|
|
struct bcma_bus *bus = cc->core->bus;
|
|
@@ -65,6 +169,25 @@ static void bcma_pmu_resources_init(stru
|
|
min_msk = 0x200D;
|
|
max_msk = 0xFFFF;
|
|
break;
|
|
+ case BCMA_CHIP_ID_BCM43142:
|
|
+ min_msk = BCMA_RES_4314_LPLDO_PU |
|
|
+ BCMA_RES_4314_PMU_SLEEP_DIS |
|
|
+ BCMA_RES_4314_PMU_BG_PU |
|
|
+ BCMA_RES_4314_CBUCK_LPOM_PU |
|
|
+ BCMA_RES_4314_CBUCK_PFM_PU |
|
|
+ BCMA_RES_4314_CLDO_PU |
|
|
+ BCMA_RES_4314_LPLDO2_LVM |
|
|
+ BCMA_RES_4314_WL_PMU_PU |
|
|
+ BCMA_RES_4314_LDO3P3_PU |
|
|
+ BCMA_RES_4314_OTP_PU |
|
|
+ BCMA_RES_4314_WL_PWRSW_PU |
|
|
+ BCMA_RES_4314_LQ_AVAIL |
|
|
+ BCMA_RES_4314_LOGIC_RET |
|
|
+ BCMA_RES_4314_MEM_SLEEP |
|
|
+ BCMA_RES_4314_MACPHY_RET |
|
|
+ BCMA_RES_4314_WL_CORE_READY;
|
|
+ max_msk = 0x3FFFFFFF;
|
|
+ break;
|
|
default:
|
|
bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
|
|
bus->chipinfo.id);
|
|
@@ -76,7 +199,10 @@ static void bcma_pmu_resources_init(stru
|
|
if (max_msk)
|
|
bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
|
|
|
|
- /* Add some delay; allow resources to come up and settle. */
|
|
+ /*
|
|
+ * Add some delay; allow resources to come up and settle.
|
|
+ * Delay is required for SoC (early init).
|
|
+ */
|
|
mdelay(2);
|
|
}
|
|
|
|
@@ -101,7 +227,7 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
|
|
bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
|
|
}
|
|
|
|
-void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
|
|
+static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
|
|
{
|
|
struct bcma_bus *bus = cc->core->bus;
|
|
|
|
@@ -141,7 +267,7 @@ void bcma_pmu_workarounds(struct bcma_dr
|
|
}
|
|
}
|
|
|
|
-void bcma_pmu_init(struct bcma_drv_cc *cc)
|
|
+void bcma_pmu_early_init(struct bcma_drv_cc *cc)
|
|
{
|
|
u32 pmucap;
|
|
|
|
@@ -150,7 +276,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
|
|
|
|
bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
|
|
cc->pmu.rev, pmucap);
|
|
+}
|
|
|
|
+void bcma_pmu_init(struct bcma_drv_cc *cc)
|
|
+{
|
|
if (cc->pmu.rev == 1)
|
|
bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
|
|
~BCMA_CC_PMU_CTL_NOILPONW);
|
|
@@ -158,28 +287,45 @@ void bcma_pmu_init(struct bcma_drv_cc *c
|
|
bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
|
|
BCMA_CC_PMU_CTL_NOILPONW);
|
|
|
|
+ bcma_pmu_pll_init(cc);
|
|
bcma_pmu_resources_init(cc);
|
|
bcma_pmu_workarounds(cc);
|
|
}
|
|
|
|
-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
|
|
+u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
|
|
{
|
|
struct bcma_bus *bus = cc->core->bus;
|
|
|
|
switch (bus->chipinfo.id) {
|
|
+ case BCMA_CHIP_ID_BCM4313:
|
|
+ case BCMA_CHIP_ID_BCM43224:
|
|
+ case BCMA_CHIP_ID_BCM43225:
|
|
+ case BCMA_CHIP_ID_BCM43227:
|
|
+ case BCMA_CHIP_ID_BCM43228:
|
|
+ case BCMA_CHIP_ID_BCM4331:
|
|
+ case BCMA_CHIP_ID_BCM43421:
|
|
+ case BCMA_CHIP_ID_BCM43428:
|
|
+ case BCMA_CHIP_ID_BCM43431:
|
|
case BCMA_CHIP_ID_BCM4716:
|
|
- case BCMA_CHIP_ID_BCM4748:
|
|
case BCMA_CHIP_ID_BCM47162:
|
|
- case BCMA_CHIP_ID_BCM4313:
|
|
- case BCMA_CHIP_ID_BCM5357:
|
|
+ case BCMA_CHIP_ID_BCM4748:
|
|
case BCMA_CHIP_ID_BCM4749:
|
|
+ case BCMA_CHIP_ID_BCM5357:
|
|
case BCMA_CHIP_ID_BCM53572:
|
|
+ case BCMA_CHIP_ID_BCM6362:
|
|
/* always 20Mhz */
|
|
return 20000 * 1000;
|
|
- case BCMA_CHIP_ID_BCM5356:
|
|
case BCMA_CHIP_ID_BCM4706:
|
|
+ case BCMA_CHIP_ID_BCM5356:
|
|
/* always 25Mhz */
|
|
return 25000 * 1000;
|
|
+ case BCMA_CHIP_ID_BCM43460:
|
|
+ case BCMA_CHIP_ID_BCM4352:
|
|
+ case BCMA_CHIP_ID_BCM4360:
|
|
+ if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
|
|
+ return 40000 * 1000;
|
|
+ else
|
|
+ return 20000 * 1000;
|
|
default:
|
|
bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
|
|
bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
|
|
@@ -190,7 +336,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
|
|
/* Find the output of the "m" pll divider given pll controls that start with
|
|
* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
|
|
*/
|
|
-static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
|
|
+static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
|
|
{
|
|
u32 tmp, div, ndiv, p1, p2, fc;
|
|
struct bcma_bus *bus = cc->core->bus;
|
|
@@ -219,14 +365,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
|
|
ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
|
|
|
|
/* Do calculation in Mhz */
|
|
- fc = bcma_pmu_alp_clock(cc) / 1000000;
|
|
+ fc = bcma_pmu_get_alp_clock(cc) / 1000000;
|
|
fc = (p1 * ndiv * fc) / p2;
|
|
|
|
/* Return clock in Hertz */
|
|
return (fc / div) * 1000000;
|
|
}
|
|
|
|
-static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
|
|
+static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
|
|
{
|
|
u32 tmp, ndiv, p1div, p2div;
|
|
u32 clock;
|
|
@@ -257,7 +403,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
|
|
}
|
|
|
|
/* query bus clock frequency for PMU-enabled chipcommon */
|
|
-u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
|
|
+u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
|
|
{
|
|
struct bcma_bus *bus = cc->core->bus;
|
|
|
|
@@ -265,40 +411,43 @@ u32 bcma_pmu_get_clockcontrol(struct bcm
|
|
case BCMA_CHIP_ID_BCM4716:
|
|
case BCMA_CHIP_ID_BCM4748:
|
|
case BCMA_CHIP_ID_BCM47162:
|
|
- return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
|
|
- BCMA_CC_PMU5_MAINPLL_SSB);
|
|
+ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
|
|
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
|
case BCMA_CHIP_ID_BCM5356:
|
|
- return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
|
|
- BCMA_CC_PMU5_MAINPLL_SSB);
|
|
+ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
|
|
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
|
case BCMA_CHIP_ID_BCM5357:
|
|
case BCMA_CHIP_ID_BCM4749:
|
|
- return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
|
|
- BCMA_CC_PMU5_MAINPLL_SSB);
|
|
+ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
|
|
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
|
case BCMA_CHIP_ID_BCM4706:
|
|
- return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
|
|
- BCMA_CC_PMU5_MAINPLL_SSB);
|
|
+ return bcma_pmu_pll_clock_bcm4706(cc,
|
|
+ BCMA_CC_PMU4706_MAINPLL_PLL0,
|
|
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
|
case BCMA_CHIP_ID_BCM53572:
|
|
return 75000000;
|
|
default:
|
|
- bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
|
|
+ bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
|
|
bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
|
|
}
|
|
return BCMA_CC_PMU_HT_CLOCK;
|
|
}
|
|
+EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
|
|
|
|
/* query cpu clock frequency for PMU-enabled chipcommon */
|
|
-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
|
|
+u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
|
|
{
|
|
struct bcma_bus *bus = cc->core->bus;
|
|
|
|
if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
|
|
return 300000000;
|
|
|
|
+ /* New PMUs can have different clock for bus and CPU */
|
|
if (cc->pmu.rev >= 5) {
|
|
u32 pll;
|
|
switch (bus->chipinfo.id) {
|
|
case BCMA_CHIP_ID_BCM4706:
|
|
- return bcma_pmu_clock_bcm4706(cc,
|
|
+ return bcma_pmu_pll_clock_bcm4706(cc,
|
|
BCMA_CC_PMU4706_MAINPLL_PLL0,
|
|
BCMA_CC_PMU5_MAINPLL_CPU);
|
|
case BCMA_CHIP_ID_BCM5356:
|
|
@@ -313,10 +462,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
|
|
break;
|
|
}
|
|
|
|
- return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
|
|
+ return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
|
|
}
|
|
|
|
- return bcma_pmu_get_clockcontrol(cc);
|
|
+ /* On old PMUs CPU has the same clock as the bus */
|
|
+ return bcma_pmu_get_bus_clock(cc);
|
|
}
|
|
|
|
static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
|
|
@@ -362,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
|
|
tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
|
|
bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
|
|
|
|
- tmp = 1 << 10;
|
|
+ tmp = BCMA_CC_PMU_CTL_PLL_UPD;
|
|
break;
|
|
|
|
case BCMA_CHIP_ID_BCM4331:
|
|
@@ -383,7 +533,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
|
|
0x03000a08);
|
|
}
|
|
- tmp = 1 << 10;
|
|
+ tmp = BCMA_CC_PMU_CTL_PLL_UPD;
|
|
break;
|
|
|
|
case BCMA_CHIP_ID_BCM43224:
|
|
@@ -416,7 +566,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
|
|
0x88888815);
|
|
}
|
|
- tmp = 1 << 10;
|
|
+ tmp = BCMA_CC_PMU_CTL_PLL_UPD;
|
|
break;
|
|
|
|
case BCMA_CHIP_ID_BCM4716:
|
|
@@ -450,7 +600,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
|
|
0x88888815);
|
|
}
|
|
|
|
- tmp = 3 << 9;
|
|
+ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
|
|
break;
|
|
|
|
case BCMA_CHIP_ID_BCM43227:
|
|
@@ -486,7 +636,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
|
|
0x88888815);
|
|
}
|
|
- tmp = 1 << 10;
|
|
+ tmp = BCMA_CC_PMU_CTL_PLL_UPD;
|
|
break;
|
|
default:
|
|
bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
|
|
--- a/drivers/bcma/driver_chipcommon_sflash.c
|
|
+++ b/drivers/bcma/driver_chipcommon_sflash.c
|
|
@@ -5,15 +5,161 @@
|
|
* Licensed under the GNU/GPL. See COPYING for details.
|
|
*/
|
|
|
|
+#include "bcma_private.h"
|
|
+
|
|
+#include <linux/platform_device.h>
|
|
#include <linux/bcma/bcma.h>
|
|
-#include <linux/bcma/bcma_driver_chipcommon.h>
|
|
-#include <linux/delay.h>
|
|
|
|
-#include "bcma_private.h"
|
|
+static struct resource bcma_sflash_resource = {
|
|
+ .name = "bcma_sflash",
|
|
+ .start = BCMA_SOC_FLASH2,
|
|
+ .end = 0,
|
|
+ .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
|
|
+};
|
|
+
|
|
+struct platform_device bcma_sflash_dev = {
|
|
+ .name = "bcma_sflash",
|
|
+ .resource = &bcma_sflash_resource,
|
|
+ .num_resources = 1,
|
|
+};
|
|
+
|
|
+struct bcma_sflash_tbl_e {
|
|
+ char *name;
|
|
+ u32 id;
|
|
+ u32 blocksize;
|
|
+ u16 numblocks;
|
|
+};
|
|
+
|
|
+static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
|
|
+ { "M25P20", 0x11, 0x10000, 4, },
|
|
+ { "M25P40", 0x12, 0x10000, 8, },
|
|
+
|
|
+ { "M25P16", 0x14, 0x10000, 32, },
|
|
+ { "M25P32", 0x15, 0x10000, 64, },
|
|
+ { "M25P64", 0x16, 0x10000, 128, },
|
|
+ { "M25FL128", 0x17, 0x10000, 256, },
|
|
+ { 0 },
|
|
+};
|
|
+
|
|
+static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
|
|
+ { "SST25WF512", 1, 0x1000, 16, },
|
|
+ { "SST25VF512", 0x48, 0x1000, 16, },
|
|
+ { "SST25WF010", 2, 0x1000, 32, },
|
|
+ { "SST25VF010", 0x49, 0x1000, 32, },
|
|
+ { "SST25WF020", 3, 0x1000, 64, },
|
|
+ { "SST25VF020", 0x43, 0x1000, 64, },
|
|
+ { "SST25WF040", 4, 0x1000, 128, },
|
|
+ { "SST25VF040", 0x44, 0x1000, 128, },
|
|
+ { "SST25VF040B", 0x8d, 0x1000, 128, },
|
|
+ { "SST25WF080", 5, 0x1000, 256, },
|
|
+ { "SST25VF080B", 0x8e, 0x1000, 256, },
|
|
+ { "SST25VF016", 0x41, 0x1000, 512, },
|
|
+ { "SST25VF032", 0x4a, 0x1000, 1024, },
|
|
+ { "SST25VF064", 0x4b, 0x1000, 2048, },
|
|
+ { 0 },
|
|
+};
|
|
+
|
|
+static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
|
|
+ { "AT45DB011", 0xc, 256, 512, },
|
|
+ { "AT45DB021", 0x14, 256, 1024, },
|
|
+ { "AT45DB041", 0x1c, 256, 2048, },
|
|
+ { "AT45DB081", 0x24, 256, 4096, },
|
|
+ { "AT45DB161", 0x2c, 512, 4096, },
|
|
+ { "AT45DB321", 0x34, 512, 8192, },
|
|
+ { "AT45DB642", 0x3c, 1024, 8192, },
|
|
+ { 0 },
|
|
+};
|
|
+
|
|
+static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
|
|
+{
|
|
+ int i;
|
|
+ bcma_cc_write32(cc, BCMA_CC_FLASHCTL,
|
|
+ BCMA_CC_FLASHCTL_START | opcode);
|
|
+ for (i = 0; i < 1000; i++) {
|
|
+ if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) &
|
|
+ BCMA_CC_FLASHCTL_BUSY))
|
|
+ return;
|
|
+ cpu_relax();
|
|
+ }
|
|
+ bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
|
|
+}
|
|
|
|
/* Initialize serial flash access */
|
|
int bcma_sflash_init(struct bcma_drv_cc *cc)
|
|
{
|
|
- bcma_err(cc->core->bus, "Serial flash support is broken\n");
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+ struct bcma_sflash *sflash = &cc->sflash;
|
|
+ const struct bcma_sflash_tbl_e *e;
|
|
+ u32 id, id2;
|
|
+
|
|
+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
|
|
+ case BCMA_CC_FLASHT_STSER:
|
|
+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP);
|
|
+
|
|
+ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0);
|
|
+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
|
|
+ id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
|
|
+
|
|
+ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1);
|
|
+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
|
|
+ id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
|
|
+
|
|
+ switch (id) {
|
|
+ case 0xbf:
|
|
+ for (e = bcma_sflash_sst_tbl; e->name; e++) {
|
|
+ if (e->id == id2)
|
|
+ break;
|
|
+ }
|
|
+ break;
|
|
+ case 0x13:
|
|
+ return -ENOTSUPP;
|
|
+ default:
|
|
+ for (e = bcma_sflash_st_tbl; e->name; e++) {
|
|
+ if (e->id == id)
|
|
+ break;
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+ if (!e->name) {
|
|
+ bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2);
|
|
+ return -ENOTSUPP;
|
|
+ }
|
|
+
|
|
+ break;
|
|
+ case BCMA_CC_FLASHT_ATSER:
|
|
+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
|
|
+ id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c;
|
|
+
|
|
+ for (e = bcma_sflash_at_tbl; e->name; e++) {
|
|
+ if (e->id == id)
|
|
+ break;
|
|
+ }
|
|
+ if (!e->name) {
|
|
+ bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id);
|
|
+ return -ENOTSUPP;
|
|
+ }
|
|
+
|
|
+ break;
|
|
+ default:
|
|
+ bcma_err(bus, "Unsupported flash type\n");
|
|
+ return -ENOTSUPP;
|
|
+ }
|
|
+
|
|
+ sflash->window = BCMA_SOC_FLASH2;
|
|
+ sflash->blocksize = e->blocksize;
|
|
+ sflash->numblocks = e->numblocks;
|
|
+ sflash->size = sflash->blocksize * sflash->numblocks;
|
|
+ sflash->present = true;
|
|
+
|
|
+ bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
|
|
+ e->name, sflash->size / 1024, sflash->blocksize,
|
|
+ sflash->numblocks);
|
|
+
|
|
+ /* Prepare platform device, but don't register it yet. It's too early,
|
|
+ * malloc (required by device_private_init) is not available yet. */
|
|
+ bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start +
|
|
+ sflash->size;
|
|
+ bcma_sflash_dev.dev.platform_data = sflash;
|
|
+
|
|
return 0;
|
|
}
|
|
--- /dev/null
|
|
+++ b/drivers/bcma/driver_gpio.c
|
|
@@ -0,0 +1,114 @@
|
|
+/*
|
|
+ * Broadcom specific AMBA
|
|
+ * GPIO driver
|
|
+ *
|
|
+ * Copyright 2011, Broadcom Corporation
|
|
+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
|
|
+ *
|
|
+ * Licensed under the GNU/GPL. See COPYING for details.
|
|
+ */
|
|
+
|
|
+#include <linux/gpio.h>
|
|
+#include <linux/export.h>
|
|
+#include <linux/bcma/bcma.h>
|
|
+
|
|
+#include "bcma_private.h"
|
|
+
|
|
+static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
|
|
+{
|
|
+ return container_of(chip, struct bcma_drv_cc, gpio);
|
|
+}
|
|
+
|
|
+static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
|
|
+{
|
|
+ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
|
|
+
|
|
+ return !!bcma_chipco_gpio_in(cc, 1 << gpio);
|
|
+}
|
|
+
|
|
+static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
|
|
+ int value)
|
|
+{
|
|
+ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
|
|
+
|
|
+ bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
|
|
+}
|
|
+
|
|
+static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
|
|
+{
|
|
+ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
|
|
+
|
|
+ bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
|
|
+ int value)
|
|
+{
|
|
+ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
|
|
+
|
|
+ bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
|
|
+ bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
|
|
+{
|
|
+ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
|
|
+
|
|
+ bcma_chipco_gpio_control(cc, 1 << gpio, 0);
|
|
+ /* clear pulldown */
|
|
+ bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
|
|
+ /* Set pullup */
|
|
+ bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
|
|
+{
|
|
+ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
|
|
+
|
|
+ /* clear pullup */
|
|
+ bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
|
|
+}
|
|
+
|
|
+static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
|
|
+{
|
|
+ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
|
|
+
|
|
+ if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
|
|
+ return bcma_core_irq(cc->core);
|
|
+ else
|
|
+ return -EINVAL;
|
|
+}
|
|
+
|
|
+int bcma_gpio_init(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ struct gpio_chip *chip = &cc->gpio;
|
|
+
|
|
+ chip->label = "bcma_gpio";
|
|
+ chip->owner = THIS_MODULE;
|
|
+ chip->request = bcma_gpio_request;
|
|
+ chip->free = bcma_gpio_free;
|
|
+ chip->get = bcma_gpio_get_value;
|
|
+ chip->set = bcma_gpio_set_value;
|
|
+ chip->direction_input = bcma_gpio_direction_input;
|
|
+ chip->direction_output = bcma_gpio_direction_output;
|
|
+ chip->to_irq = bcma_gpio_to_irq;
|
|
+ chip->ngpio = 16;
|
|
+ /* There is just one SoC in one device and its GPIO addresses should be
|
|
+ * deterministic to address them more easily. The other buses could get
|
|
+ * a random base number. */
|
|
+ if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
|
|
+ chip->base = 0;
|
|
+ else
|
|
+ chip->base = -1;
|
|
+
|
|
+ return gpiochip_add(chip);
|
|
+}
|
|
+
|
|
+int bcma_gpio_unregister(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ return gpiochip_remove(&cc->gpio);
|
|
+}
|
|
--- a/drivers/bcma/driver_mips.c
|
|
+++ b/drivers/bcma/driver_mips.c
|
|
@@ -14,11 +14,33 @@
|
|
|
|
#include <linux/bcma/bcma.h>
|
|
|
|
+#include <linux/mtd/physmap.h>
|
|
+#include <linux/platform_device.h>
|
|
#include <linux/serial.h>
|
|
#include <linux/serial_core.h>
|
|
#include <linux/serial_reg.h>
|
|
#include <linux/time.h>
|
|
|
|
+static const char * const part_probes[] = { "bcm47xxpart", NULL };
|
|
+
|
|
+static struct physmap_flash_data bcma_pflash_data = {
|
|
+ .part_probe_types = part_probes,
|
|
+};
|
|
+
|
|
+static struct resource bcma_pflash_resource = {
|
|
+ .name = "bcma_pflash",
|
|
+ .flags = IORESOURCE_MEM,
|
|
+};
|
|
+
|
|
+struct platform_device bcma_pflash_dev = {
|
|
+ .name = "physmap-flash",
|
|
+ .dev = {
|
|
+ .platform_data = &bcma_pflash_data,
|
|
+ },
|
|
+ .resource = &bcma_pflash_resource,
|
|
+ .num_resources = 1,
|
|
+};
|
|
+
|
|
/* The 47162a0 hangs when reading MIPS DMP registers registers */
|
|
static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
|
|
{
|
|
@@ -74,28 +96,41 @@ static u32 bcma_core_mips_irqflag(struct
|
|
return dev->core_index;
|
|
flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
|
|
|
|
- return flag & 0x1F;
|
|
+ if (flag)
|
|
+ return flag & 0x1F;
|
|
+ else
|
|
+ return 0x3f;
|
|
}
|
|
|
|
/* Get the MIPS IRQ assignment for a specified device.
|
|
* If unassigned, 0 is returned.
|
|
+ * If disabled, 5 is returned.
|
|
+ * If not supported, 6 is returned.
|
|
*/
|
|
-unsigned int bcma_core_mips_irq(struct bcma_device *dev)
|
|
+static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
|
|
{
|
|
struct bcma_device *mdev = dev->bus->drv_mips.core;
|
|
u32 irqflag;
|
|
unsigned int irq;
|
|
|
|
irqflag = bcma_core_mips_irqflag(dev);
|
|
+ if (irqflag == 0x3f)
|
|
+ return 6;
|
|
|
|
- for (irq = 1; irq <= 4; irq++)
|
|
+ for (irq = 0; irq <= 4; irq++)
|
|
if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
|
|
(1 << irqflag))
|
|
return irq;
|
|
|
|
- return 0;
|
|
+ return 5;
|
|
+}
|
|
+
|
|
+unsigned int bcma_core_irq(struct bcma_device *dev)
|
|
+{
|
|
+ unsigned int mips_irq = bcma_core_mips_irq(dev);
|
|
+ return mips_irq <= 4 ? mips_irq + 2 : 0;
|
|
}
|
|
-EXPORT_SYMBOL(bcma_core_mips_irq);
|
|
+EXPORT_SYMBOL(bcma_core_irq);
|
|
|
|
static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
|
|
{
|
|
@@ -114,8 +149,8 @@ static void bcma_core_mips_set_irq(struc
|
|
bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
|
|
bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
|
|
~(1 << irqflag));
|
|
- else
|
|
- bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
|
|
+ else if (oldirq != 5)
|
|
+ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
|
|
|
|
/* assign the new one */
|
|
if (irq == 0) {
|
|
@@ -123,9 +158,9 @@ static void bcma_core_mips_set_irq(struc
|
|
bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
|
|
(1 << irqflag));
|
|
} else {
|
|
- u32 oldirqflag = bcma_read32(mdev,
|
|
- BCMA_MIPS_MIPS74K_INTMASK(irq));
|
|
- if (oldirqflag) {
|
|
+ u32 irqinitmask = bcma_read32(mdev,
|
|
+ BCMA_MIPS_MIPS74K_INTMASK(irq));
|
|
+ if (irqinitmask) {
|
|
struct bcma_device *core;
|
|
|
|
/* backplane irq line is in use, find out who uses
|
|
@@ -133,7 +168,7 @@ static void bcma_core_mips_set_irq(struc
|
|
*/
|
|
list_for_each_entry(core, &bus->cores, list) {
|
|
if ((1 << bcma_core_mips_irqflag(core)) ==
|
|
- oldirqflag) {
|
|
+ irqinitmask) {
|
|
bcma_core_mips_set_irq(core, 0);
|
|
break;
|
|
}
|
|
@@ -143,15 +178,31 @@ static void bcma_core_mips_set_irq(struc
|
|
1 << irqflag);
|
|
}
|
|
|
|
- bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
|
|
- dev->id.id, oldirq + 2, irq + 2);
|
|
+ bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
|
|
+ dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
|
|
+}
|
|
+
|
|
+static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
|
|
+ u16 coreid, u8 unit)
|
|
+{
|
|
+ struct bcma_device *core;
|
|
+
|
|
+ core = bcma_find_core_unit(bus, coreid, unit);
|
|
+ if (!core) {
|
|
+ bcma_warn(bus,
|
|
+ "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
|
|
+ coreid, unit);
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ bcma_core_mips_set_irq(core, irq);
|
|
}
|
|
|
|
static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
|
|
{
|
|
int i;
|
|
static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
|
|
- printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
|
|
+ printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
|
|
for (i = 0; i <= 6; i++)
|
|
printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
|
|
printk("\n");
|
|
@@ -171,7 +222,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
|
|
struct bcma_bus *bus = mcore->core->bus;
|
|
|
|
if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
|
|
- return bcma_pmu_get_clockcpu(&bus->drv_cc);
|
|
+ return bcma_pmu_get_cpu_clock(&bus->drv_cc);
|
|
|
|
bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
|
|
return 0;
|
|
@@ -181,85 +232,143 @@ EXPORT_SYMBOL(bcma_cpu_clock);
|
|
static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
|
|
{
|
|
struct bcma_bus *bus = mcore->core->bus;
|
|
+ struct bcma_drv_cc *cc = &bus->drv_cc;
|
|
+ struct bcma_pflash *pflash = &cc->pflash;
|
|
|
|
- switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
|
|
+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
|
|
case BCMA_CC_FLASHT_STSER:
|
|
case BCMA_CC_FLASHT_ATSER:
|
|
bcma_debug(bus, "Found serial flash\n");
|
|
- bcma_sflash_init(&bus->drv_cc);
|
|
+ bcma_sflash_init(cc);
|
|
break;
|
|
case BCMA_CC_FLASHT_PARA:
|
|
bcma_debug(bus, "Found parallel flash\n");
|
|
- bus->drv_cc.pflash.window = 0x1c000000;
|
|
- bus->drv_cc.pflash.window_size = 0x02000000;
|
|
+ pflash->present = true;
|
|
+ pflash->window = BCMA_SOC_FLASH2;
|
|
+ pflash->window_size = BCMA_SOC_FLASH2_SZ;
|
|
|
|
- if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
|
|
+ if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
|
|
BCMA_CC_FLASH_CFG_DS) == 0)
|
|
- bus->drv_cc.pflash.buswidth = 1;
|
|
+ pflash->buswidth = 1;
|
|
else
|
|
- bus->drv_cc.pflash.buswidth = 2;
|
|
+ pflash->buswidth = 2;
|
|
+
|
|
+ bcma_pflash_data.width = pflash->buswidth;
|
|
+ bcma_pflash_resource.start = pflash->window;
|
|
+ bcma_pflash_resource.end = pflash->window + pflash->window_size;
|
|
+
|
|
break;
|
|
default:
|
|
bcma_err(bus, "Flash type not supported\n");
|
|
}
|
|
|
|
- if (bus->drv_cc.core->id.rev == 38 ||
|
|
+ if (cc->core->id.rev == 38 ||
|
|
bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
|
|
- if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
|
|
+ if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
|
|
bcma_debug(bus, "Found NAND flash\n");
|
|
- bcma_nflash_init(&bus->drv_cc);
|
|
+ bcma_nflash_init(cc);
|
|
}
|
|
}
|
|
}
|
|
|
|
+void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
|
|
+{
|
|
+ struct bcma_bus *bus = mcore->core->bus;
|
|
+
|
|
+ if (mcore->early_setup_done)
|
|
+ return;
|
|
+
|
|
+ bcma_chipco_serial_init(&bus->drv_cc);
|
|
+ bcma_core_mips_flash_detect(mcore);
|
|
+
|
|
+ mcore->early_setup_done = true;
|
|
+}
|
|
+
|
|
+static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
|
|
+{
|
|
+ struct bcma_device *cpu, *pcie, *i2s;
|
|
+
|
|
+ /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
|
|
+ * (IRQ flags > 7 are ignored when setting the interrupt masks)
|
|
+ */
|
|
+ if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
|
|
+ bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
|
|
+ return;
|
|
+
|
|
+ cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
|
|
+ pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
|
|
+ i2s = bcma_find_core(bus, BCMA_CORE_I2S);
|
|
+ if (cpu && pcie && i2s &&
|
|
+ bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
|
|
+ bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
|
|
+ bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
|
|
+ bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
|
|
+ bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
|
|
+ bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
|
|
+ bcma_debug(bus,
|
|
+ "Moved i2s interrupt to oob line 7 instead of 8\n");
|
|
+ }
|
|
+}
|
|
+
|
|
void bcma_core_mips_init(struct bcma_drv_mips *mcore)
|
|
{
|
|
struct bcma_bus *bus;
|
|
struct bcma_device *core;
|
|
bus = mcore->core->bus;
|
|
|
|
- bcma_info(bus, "Initializing MIPS core...\n");
|
|
+ if (mcore->setup_done)
|
|
+ return;
|
|
|
|
- if (!mcore->setup_done)
|
|
- mcore->assigned_irqs = 1;
|
|
+ bcma_debug(bus, "Initializing MIPS core...\n");
|
|
|
|
- /* Assign IRQs to all cores on the bus */
|
|
- list_for_each_entry(core, &bus->cores, list) {
|
|
- int mips_irq;
|
|
- if (core->irq)
|
|
- continue;
|
|
-
|
|
- mips_irq = bcma_core_mips_irq(core);
|
|
- if (mips_irq > 4)
|
|
- core->irq = 0;
|
|
- else
|
|
- core->irq = mips_irq + 2;
|
|
- if (core->irq > 5)
|
|
- continue;
|
|
- switch (core->id.id) {
|
|
- case BCMA_CORE_PCI:
|
|
- case BCMA_CORE_PCIE:
|
|
- case BCMA_CORE_ETHERNET:
|
|
- case BCMA_CORE_ETHERNET_GBIT:
|
|
- case BCMA_CORE_MAC_GBIT:
|
|
- case BCMA_CORE_80211:
|
|
- case BCMA_CORE_USB20_HOST:
|
|
- /* These devices get their own IRQ line if available,
|
|
- * the rest goes on IRQ0
|
|
- */
|
|
- if (mcore->assigned_irqs <= 4)
|
|
- bcma_core_mips_set_irq(core,
|
|
- mcore->assigned_irqs++);
|
|
- break;
|
|
+ bcma_core_mips_early_init(mcore);
|
|
+
|
|
+ bcma_fix_i2s_irqflag(bus);
|
|
+
|
|
+ switch (bus->chipinfo.id) {
|
|
+ case BCMA_CHIP_ID_BCM4716:
|
|
+ case BCMA_CHIP_ID_BCM4748:
|
|
+ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
|
|
+ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
|
|
+ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
|
|
+ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
|
|
+ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
|
|
+ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
|
|
+ break;
|
|
+ case BCMA_CHIP_ID_BCM5356:
|
|
+ case BCMA_CHIP_ID_BCM47162:
|
|
+ case BCMA_CHIP_ID_BCM53572:
|
|
+ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
|
|
+ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
|
|
+ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
|
|
+ break;
|
|
+ case BCMA_CHIP_ID_BCM5357:
|
|
+ case BCMA_CHIP_ID_BCM4749:
|
|
+ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
|
|
+ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
|
|
+ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
|
|
+ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
|
|
+ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
|
|
+ break;
|
|
+ case BCMA_CHIP_ID_BCM4706:
|
|
+ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
|
|
+ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
|
|
+ 0);
|
|
+ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
|
|
+ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
|
|
+ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
|
|
+ 0);
|
|
+ break;
|
|
+ default:
|
|
+ list_for_each_entry(core, &bus->cores, list) {
|
|
+ core->irq = bcma_core_irq(core);
|
|
}
|
|
+ bcma_err(bus,
|
|
+ "Unknown device (0x%x) found, can not configure IRQs\n",
|
|
+ bus->chipinfo.id);
|
|
}
|
|
- bcma_info(bus, "IRQ reconfiguration done\n");
|
|
+ bcma_debug(bus, "IRQ reconfiguration done\n");
|
|
bcma_core_mips_dump_irq(bus);
|
|
|
|
- if (mcore->setup_done)
|
|
- return;
|
|
-
|
|
- bcma_chipco_serial_init(&bus->drv_cc);
|
|
- bcma_core_mips_flash_detect(mcore);
|
|
mcore->setup_done = true;
|
|
}
|
|
--- a/drivers/bcma/driver_pci.c
|
|
+++ b/drivers/bcma/driver_pci.c
|
|
@@ -51,7 +51,7 @@ static void bcma_pcie_mdio_set_phy(struc
|
|
v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
|
|
if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
|
|
break;
|
|
- msleep(1);
|
|
+ usleep_range(1000, 2000);
|
|
}
|
|
}
|
|
|
|
@@ -92,7 +92,7 @@ static u16 bcma_pcie_mdio_read(struct bc
|
|
ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
|
|
break;
|
|
}
|
|
- msleep(1);
|
|
+ usleep_range(1000, 2000);
|
|
}
|
|
pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
|
|
return ret;
|
|
@@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct
|
|
v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
|
|
if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
|
|
break;
|
|
- msleep(1);
|
|
+ usleep_range(1000, 2000);
|
|
}
|
|
pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
|
|
}
|
|
--- a/drivers/bcma/driver_pci_host.c
|
|
+++ b/drivers/bcma/driver_pci_host.c
|
|
@@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
|
|
chipid_top != 0x5300)
|
|
return false;
|
|
|
|
- if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
|
|
- bcma_info(bus, "This PCI core is disabled and not working\n");
|
|
- return false;
|
|
- }
|
|
-
|
|
bcma_core_enable(pc->core, 0);
|
|
|
|
return !mips_busprobe32(tmp, pc->core->io_addr);
|
|
@@ -99,19 +94,19 @@ static int bcma_extpci_read_config(struc
|
|
if (dev == 0) {
|
|
/* we support only two functions on device 0 */
|
|
if (func > 1)
|
|
- return -EINVAL;
|
|
+ goto out;
|
|
|
|
/* accesses to config registers with offsets >= 256
|
|
* requires indirect access.
|
|
*/
|
|
if (off >= PCI_CONFIG_SPACE_SIZE) {
|
|
addr = (func << 12);
|
|
- addr |= (off & 0x0FFF);
|
|
+ addr |= (off & 0x0FFC);
|
|
val = bcma_pcie_read_config(pc, addr);
|
|
} else {
|
|
addr = BCMA_CORE_PCI_PCICFG0;
|
|
addr |= (func << 8);
|
|
- addr |= (off & 0xfc);
|
|
+ addr |= (off & 0xFC);
|
|
val = pcicore_read32(pc, addr);
|
|
}
|
|
} else {
|
|
@@ -124,11 +119,9 @@ static int bcma_extpci_read_config(struc
|
|
goto out;
|
|
|
|
if (mips_busprobe32(val, mmio)) {
|
|
- val = 0xffffffff;
|
|
+ val = 0xFFFFFFFF;
|
|
goto unmap;
|
|
}
|
|
-
|
|
- val = readl(mmio);
|
|
}
|
|
val >>= (8 * (off & 3));
|
|
|
|
@@ -156,7 +149,7 @@ static int bcma_extpci_write_config(stru
|
|
const void *buf, int len)
|
|
{
|
|
int err = -EINVAL;
|
|
- u32 addr = 0, val = 0;
|
|
+ u32 addr, val;
|
|
void __iomem *mmio = 0;
|
|
u16 chipid = pc->core->bus->chipinfo.id;
|
|
|
|
@@ -164,16 +157,22 @@ static int bcma_extpci_write_config(stru
|
|
if (unlikely(len != 1 && len != 2 && len != 4))
|
|
goto out;
|
|
if (dev == 0) {
|
|
+ /* we support only two functions on device 0 */
|
|
+ if (func > 1)
|
|
+ goto out;
|
|
+
|
|
/* accesses to config registers with offsets >= 256
|
|
* requires indirect access.
|
|
*/
|
|
- if (off < PCI_CONFIG_SPACE_SIZE) {
|
|
- addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
|
|
+ if (off >= PCI_CONFIG_SPACE_SIZE) {
|
|
+ addr = (func << 12);
|
|
+ addr |= (off & 0x0FFC);
|
|
+ val = bcma_pcie_read_config(pc, addr);
|
|
+ } else {
|
|
+ addr = BCMA_CORE_PCI_PCICFG0;
|
|
addr |= (func << 8);
|
|
- addr |= (off & 0xfc);
|
|
- mmio = ioremap_nocache(addr, sizeof(val));
|
|
- if (!mmio)
|
|
- goto out;
|
|
+ addr |= (off & 0xFC);
|
|
+ val = pcicore_read32(pc, addr);
|
|
}
|
|
} else {
|
|
addr = bcma_get_cfgspace_addr(pc, dev, func, off);
|
|
@@ -185,19 +184,17 @@ static int bcma_extpci_write_config(stru
|
|
goto out;
|
|
|
|
if (mips_busprobe32(val, mmio)) {
|
|
- val = 0xffffffff;
|
|
+ val = 0xFFFFFFFF;
|
|
goto unmap;
|
|
}
|
|
}
|
|
|
|
switch (len) {
|
|
case 1:
|
|
- val = readl(mmio);
|
|
val &= ~(0xFF << (8 * (off & 3)));
|
|
val |= *((const u8 *)buf) << (8 * (off & 3));
|
|
break;
|
|
case 2:
|
|
- val = readl(mmio);
|
|
val &= ~(0xFFFF << (8 * (off & 3)));
|
|
val |= *((const u16 *)buf) << (8 * (off & 3));
|
|
break;
|
|
@@ -205,13 +202,14 @@ static int bcma_extpci_write_config(stru
|
|
val = *((const u32 *)buf);
|
|
break;
|
|
}
|
|
- if (dev == 0 && !addr) {
|
|
+ if (dev == 0) {
|
|
/* accesses to config registers with offsets >= 256
|
|
* requires indirect access.
|
|
*/
|
|
- addr = (func << 12);
|
|
- addr |= (off & 0x0FFF);
|
|
- bcma_pcie_write_config(pc, addr, val);
|
|
+ if (off >= PCI_CONFIG_SPACE_SIZE)
|
|
+ bcma_pcie_write_config(pc, addr, val);
|
|
+ else
|
|
+ pcicore_write32(pc, addr, val);
|
|
} else {
|
|
writel(val, mmio);
|
|
|
|
@@ -282,7 +280,7 @@ static u8 __devinit bcma_find_pci_capabi
|
|
/* check for Header type 0 */
|
|
bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
|
|
sizeof(u8));
|
|
- if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
|
|
+ if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
|
|
return cap_ptr;
|
|
|
|
/* check if the capability pointer field exists */
|
|
@@ -396,12 +394,19 @@ void __devinit bcma_core_pci_hostmode_in
|
|
|
|
bcma_info(bus, "PCIEcore in host mode found\n");
|
|
|
|
+ if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
|
|
+ bcma_info(bus, "This PCIE core is disabled and not working\n");
|
|
+ return;
|
|
+ }
|
|
+
|
|
pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
|
|
if (!pc_host) {
|
|
bcma_err(bus, "can not allocate memory");
|
|
return;
|
|
}
|
|
|
|
+ spin_lock_init(&pc_host->cfgspace_lock);
|
|
+
|
|
pc->host_controller = pc_host;
|
|
pc_host->pci_controller.io_resource = &pc_host->io_resource;
|
|
pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
|
|
@@ -425,9 +430,9 @@ void __devinit bcma_core_pci_hostmode_in
|
|
pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
|
|
|
|
/* Reset RC */
|
|
- udelay(3000);
|
|
+ usleep_range(3000, 5000);
|
|
pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
|
|
- udelay(1000);
|
|
+ msleep(50);
|
|
pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
|
|
BCMA_CORE_PCI_CTL_RST_OE);
|
|
|
|
@@ -452,6 +457,8 @@ void __devinit bcma_core_pci_hostmode_in
|
|
pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
|
|
pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
|
|
BCMA_SOC_PCI_MEM_SZ - 1;
|
|
+ pc_host->io_resource.start = 0x100;
|
|
+ pc_host->io_resource.end = 0x47F;
|
|
pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
|
|
pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
|
|
tmp | BCMA_SOC_PCI_MEM);
|
|
@@ -459,6 +466,8 @@ void __devinit bcma_core_pci_hostmode_in
|
|
pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
|
|
pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
|
|
BCMA_SOC_PCI_MEM_SZ - 1;
|
|
+ pc_host->io_resource.start = 0x480;
|
|
+ pc_host->io_resource.end = 0x7FF;
|
|
pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
|
|
pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
|
|
pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
|
|
@@ -481,10 +490,21 @@ void __devinit bcma_core_pci_hostmode_in
|
|
* before issuing configuration requests to PCI Express
|
|
* devices.
|
|
*/
|
|
- udelay(100000);
|
|
+ msleep(100);
|
|
|
|
bcma_core_pci_enable_crs(pc);
|
|
|
|
+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
|
|
+ bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
|
|
+ u16 val16;
|
|
+ bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
|
|
+ &val16, sizeof(val16));
|
|
+ val16 |= (2 << 5); /* Max payload size of 512 */
|
|
+ val16 |= (2 << 12); /* MRRS 512 */
|
|
+ bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
|
|
+ &val16, sizeof(val16));
|
|
+ }
|
|
+
|
|
/* Enable PCI bridge BAR0 memory & master access */
|
|
tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
|
bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
|
|
@@ -501,7 +521,7 @@ void __devinit bcma_core_pci_hostmode_in
|
|
set_io_port_base(pc_host->pci_controller.io_map_base);
|
|
/* Give some time to the PCI controller to configure itself with the new
|
|
* values. Not waiting at this point causes crashes of the machine. */
|
|
- mdelay(10);
|
|
+ usleep_range(10000, 15000);
|
|
register_pci_controller(&pc_host->pci_controller);
|
|
return;
|
|
}
|
|
@@ -534,7 +554,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
|
|
static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
|
|
{
|
|
struct resource *res;
|
|
- int pos;
|
|
+ int pos, err;
|
|
|
|
if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
|
|
/* This is not a device on the PCI-core bridge. */
|
|
@@ -547,8 +567,12 @@ static void bcma_core_pci_fixup_addresse
|
|
|
|
for (pos = 0; pos < 6; pos++) {
|
|
res = &dev->resource[pos];
|
|
- if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
|
|
- pci_assign_resource(dev, pos);
|
|
+ if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
|
|
+ err = pci_assign_resource(dev, pos);
|
|
+ if (err)
|
|
+ pr_err("PCI: Problem fixing up the addresses on %s\n",
|
|
+ pci_name(dev));
|
|
+ }
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
|
|
@@ -569,7 +593,7 @@ int bcma_core_pci_plat_dev_init(struct p
|
|
pr_info("PCI: Fixing up device %s\n", pci_name(dev));
|
|
|
|
/* Fix up interrupt lines */
|
|
- dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
|
|
+ dev->irq = bcma_core_irq(pc_host->pdev->core);
|
|
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
|
|
|
|
return 0;
|
|
@@ -588,6 +612,6 @@ int bcma_core_pci_pcibios_map_irq(const
|
|
|
|
pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
|
|
pci_ops);
|
|
- return bcma_core_mips_irq(pc_host->pdev->core) + 2;
|
|
+ return bcma_core_irq(pc_host->pdev->core);
|
|
}
|
|
EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
|
|
--- a/drivers/bcma/host_pci.c
|
|
+++ b/drivers/bcma/host_pci.c
|
|
@@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
|
|
}
|
|
|
|
#ifdef CONFIG_BCMA_BLOCKIO
|
|
-void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
|
|
- size_t count, u16 offset, u8 reg_width)
|
|
+static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
|
|
+ size_t count, u16 offset, u8 reg_width)
|
|
{
|
|
void __iomem *addr = core->bus->mmio + offset;
|
|
if (core->bus->mapped_core != core)
|
|
@@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm
|
|
}
|
|
}
|
|
|
|
-void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
|
|
- size_t count, u16 offset, u8 reg_width)
|
|
+static void bcma_host_pci_block_write(struct bcma_device *core,
|
|
+ const void *buffer, size_t count,
|
|
+ u16 offset, u8 reg_width)
|
|
{
|
|
void __iomem *addr = core->bus->mmio + offset;
|
|
if (core->bus->mapped_core != core)
|
|
@@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc
|
|
iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
|
|
}
|
|
|
|
-const struct bcma_host_ops bcma_host_pci_ops = {
|
|
+static const struct bcma_host_ops bcma_host_pci_ops = {
|
|
.read8 = bcma_host_pci_read8,
|
|
.read16 = bcma_host_pci_read16,
|
|
.read32 = bcma_host_pci_read32,
|
|
@@ -237,7 +238,7 @@ static void __devexit bcma_host_pci_remo
|
|
pci_set_drvdata(dev, NULL);
|
|
}
|
|
|
|
-#ifdef CONFIG_PM
|
|
+#ifdef CONFIG_PM_SLEEP
|
|
static int bcma_host_pci_suspend(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
@@ -260,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
|
|
bcma_host_pci_resume);
|
|
#define BCMA_PM_OPS (&bcma_pm_ops)
|
|
|
|
-#else /* CONFIG_PM */
|
|
+#else /* CONFIG_PM_SLEEP */
|
|
|
|
#define BCMA_PM_OPS NULL
|
|
|
|
-#endif /* CONFIG_PM */
|
|
+#endif /* CONFIG_PM_SLEEP */
|
|
|
|
static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
|
|
@@ -272,7 +273,9 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
|
|
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
|
|
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
|
|
{ 0, },
|
|
};
|
|
--- a/drivers/bcma/host_soc.c
|
|
+++ b/drivers/bcma/host_soc.c
|
|
@@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc
|
|
writel(value, core->io_wrap + offset);
|
|
}
|
|
|
|
-const struct bcma_host_ops bcma_host_soc_ops = {
|
|
+static const struct bcma_host_ops bcma_host_soc_ops = {
|
|
.read8 = bcma_host_soc_read8,
|
|
.read16 = bcma_host_soc_read16,
|
|
.read32 = bcma_host_soc_read32,
|
|
--- a/drivers/bcma/main.c
|
|
+++ b/drivers/bcma/main.c
|
|
@@ -7,6 +7,7 @@
|
|
|
|
#include "bcma_private.h"
|
|
#include <linux/module.h>
|
|
+#include <linux/platform_device.h>
|
|
#include <linux/bcma/bcma.h>
|
|
#include <linux/slab.h>
|
|
|
|
@@ -80,6 +81,37 @@ struct bcma_device *bcma_find_core(struc
|
|
}
|
|
EXPORT_SYMBOL_GPL(bcma_find_core);
|
|
|
|
+struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
|
|
+ u8 unit)
|
|
+{
|
|
+ struct bcma_device *core;
|
|
+
|
|
+ list_for_each_entry(core, &bus->cores, list) {
|
|
+ if (core->id.id == coreid && core->core_unit == unit)
|
|
+ return core;
|
|
+ }
|
|
+ return NULL;
|
|
+}
|
|
+
|
|
+bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
|
|
+ int timeout)
|
|
+{
|
|
+ unsigned long deadline = jiffies + timeout;
|
|
+ u32 val;
|
|
+
|
|
+ do {
|
|
+ val = bcma_read32(core, reg);
|
|
+ if ((val & mask) == value)
|
|
+ return true;
|
|
+ cpu_relax();
|
|
+ udelay(10);
|
|
+ } while (!time_after_eq(jiffies, deadline));
|
|
+
|
|
+ bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
|
|
+
|
|
+ return false;
|
|
+}
|
|
+
|
|
static void bcma_release_core_dev(struct device *dev)
|
|
{
|
|
struct bcma_device *core = container_of(dev, struct bcma_device, dev);
|
|
@@ -107,6 +139,11 @@ static int bcma_register_cores(struct bc
|
|
continue;
|
|
}
|
|
|
|
+ /* Only first GMAC core on BCM4706 is connected and working */
|
|
+ if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
|
|
+ core->core_unit > 0)
|
|
+ continue;
|
|
+
|
|
core->dev.release = bcma_release_core_dev;
|
|
core->dev.bus = &bcma_bus_type;
|
|
dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
|
|
@@ -136,6 +173,41 @@ static int bcma_register_cores(struct bc
|
|
dev_id++;
|
|
}
|
|
|
|
+#ifdef CONFIG_BCMA_DRIVER_MIPS
|
|
+ if (bus->drv_cc.pflash.present) {
|
|
+ err = platform_device_register(&bcma_pflash_dev);
|
|
+ if (err)
|
|
+ bcma_err(bus, "Error registering parallel flash\n");
|
|
+ }
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_BCMA_SFLASH
|
|
+ if (bus->drv_cc.sflash.present) {
|
|
+ err = platform_device_register(&bcma_sflash_dev);
|
|
+ if (err)
|
|
+ bcma_err(bus, "Error registering serial flash\n");
|
|
+ }
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_BCMA_NFLASH
|
|
+ if (bus->drv_cc.nflash.present) {
|
|
+ err = platform_device_register(&bcma_nflash_dev);
|
|
+ if (err)
|
|
+ bcma_err(bus, "Error registering NAND flash\n");
|
|
+ }
|
|
+#endif
|
|
+ err = bcma_gpio_init(&bus->drv_cc);
|
|
+ if (err == -ENOTSUPP)
|
|
+ bcma_debug(bus, "GPIO driver not activated\n");
|
|
+ else if (err)
|
|
+ bcma_err(bus, "Error registering GPIO driver: %i\n", err);
|
|
+
|
|
+ if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
|
|
+ err = bcma_chipco_watchdog_register(&bus->drv_cc);
|
|
+ if (err)
|
|
+ bcma_err(bus, "Error registering watchdog driver\n");
|
|
+ }
|
|
+
|
|
return 0;
|
|
}
|
|
|
|
@@ -148,6 +220,8 @@ static void bcma_unregister_cores(struct
|
|
if (core->dev_registered)
|
|
device_unregister(&core->dev);
|
|
}
|
|
+ if (bus->hosttype == BCMA_HOSTTYPE_SOC)
|
|
+ platform_device_unregister(bus->drv_cc.watchdog);
|
|
}
|
|
|
|
int __devinit bcma_bus_register(struct bcma_bus *bus)
|
|
@@ -166,6 +240,20 @@ int __devinit bcma_bus_register(struct b
|
|
return -1;
|
|
}
|
|
|
|
+ /* Early init CC core */
|
|
+ core = bcma_find_core(bus, bcma_cc_core_id(bus));
|
|
+ if (core) {
|
|
+ bus->drv_cc.core = core;
|
|
+ bcma_core_chipcommon_early_init(&bus->drv_cc);
|
|
+ }
|
|
+
|
|
+ /* Try to get SPROM */
|
|
+ err = bcma_sprom_get(bus);
|
|
+ if (err == -ENOENT) {
|
|
+ bcma_err(bus, "No SPROM available\n");
|
|
+ } else if (err)
|
|
+ bcma_err(bus, "Failed to get SPROM: %d\n", err);
|
|
+
|
|
/* Init CC core */
|
|
core = bcma_find_core(bus, bcma_cc_core_id(bus));
|
|
if (core) {
|
|
@@ -181,10 +269,17 @@ int __devinit bcma_bus_register(struct b
|
|
}
|
|
|
|
/* Init PCIE core */
|
|
- core = bcma_find_core(bus, BCMA_CORE_PCIE);
|
|
+ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
|
|
if (core) {
|
|
- bus->drv_pci.core = core;
|
|
- bcma_core_pci_init(&bus->drv_pci);
|
|
+ bus->drv_pci[0].core = core;
|
|
+ bcma_core_pci_init(&bus->drv_pci[0]);
|
|
+ }
|
|
+
|
|
+ /* Init PCIE core */
|
|
+ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
|
|
+ if (core) {
|
|
+ bus->drv_pci[1].core = core;
|
|
+ bcma_core_pci_init(&bus->drv_pci[1]);
|
|
}
|
|
|
|
/* Init GBIT MAC COMMON core */
|
|
@@ -194,13 +289,6 @@ int __devinit bcma_bus_register(struct b
|
|
bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
|
|
}
|
|
|
|
- /* Try to get SPROM */
|
|
- err = bcma_sprom_get(bus);
|
|
- if (err == -ENOENT) {
|
|
- bcma_err(bus, "No SPROM available\n");
|
|
- } else if (err)
|
|
- bcma_err(bus, "Failed to get SPROM: %d\n", err);
|
|
-
|
|
/* Register found cores */
|
|
bcma_register_cores(bus);
|
|
|
|
@@ -211,7 +299,24 @@ int __devinit bcma_bus_register(struct b
|
|
|
|
void bcma_bus_unregister(struct bcma_bus *bus)
|
|
{
|
|
+ struct bcma_device *cores[3];
|
|
+ int err;
|
|
+
|
|
+ err = bcma_gpio_unregister(&bus->drv_cc);
|
|
+ if (err == -EBUSY)
|
|
+ bcma_err(bus, "Some GPIOs are still in use.\n");
|
|
+ else if (err)
|
|
+ bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
|
|
+
|
|
+ cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
|
|
+ cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
|
|
+ cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
|
|
+
|
|
bcma_unregister_cores(bus);
|
|
+
|
|
+ kfree(cores[2]);
|
|
+ kfree(cores[1]);
|
|
+ kfree(cores[0]);
|
|
}
|
|
|
|
int __init bcma_bus_early_register(struct bcma_bus *bus,
|
|
@@ -248,18 +353,18 @@ int __init bcma_bus_early_register(struc
|
|
return -1;
|
|
}
|
|
|
|
- /* Init CC core */
|
|
+ /* Early init CC core */
|
|
core = bcma_find_core(bus, bcma_cc_core_id(bus));
|
|
if (core) {
|
|
bus->drv_cc.core = core;
|
|
- bcma_core_chipcommon_init(&bus->drv_cc);
|
|
+ bcma_core_chipcommon_early_init(&bus->drv_cc);
|
|
}
|
|
|
|
- /* Init MIPS core */
|
|
+ /* Early init MIPS core */
|
|
core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
|
|
if (core) {
|
|
bus->drv_mips.core = core;
|
|
- bcma_core_mips_init(&bus->drv_mips);
|
|
+ bcma_core_mips_early_init(&bus->drv_mips);
|
|
}
|
|
|
|
bcma_info(bus, "Early bus registered\n");
|
|
--- a/drivers/bcma/scan.c
|
|
+++ b/drivers/bcma/scan.c
|
|
@@ -84,6 +84,8 @@ static const struct bcma_device_id_name
|
|
{ BCMA_CORE_I2S, "I2S" },
|
|
{ BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
|
|
{ BCMA_CORE_SHIM, "SHIM" },
|
|
+ { BCMA_CORE_PCIE2, "PCIe Gen2" },
|
|
+ { BCMA_CORE_ARM_CR4, "ARM CR4" },
|
|
{ BCMA_CORE_DEFAULT, "Default" },
|
|
};
|
|
|
|
@@ -137,19 +139,19 @@ static void bcma_scan_switch_core(struct
|
|
addr);
|
|
}
|
|
|
|
-static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
|
|
+static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
|
|
{
|
|
u32 ent = readl(*eromptr);
|
|
(*eromptr)++;
|
|
return ent;
|
|
}
|
|
|
|
-static void bcma_erom_push_ent(u32 **eromptr)
|
|
+static void bcma_erom_push_ent(u32 __iomem **eromptr)
|
|
{
|
|
(*eromptr)--;
|
|
}
|
|
|
|
-static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
|
|
+static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
|
|
{
|
|
u32 ent = bcma_erom_get_ent(bus, eromptr);
|
|
if (!(ent & SCAN_ER_VALID))
|
|
@@ -159,14 +161,14 @@ static s32 bcma_erom_get_ci(struct bcma_
|
|
return ent;
|
|
}
|
|
|
|
-static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
|
|
+static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
|
|
{
|
|
u32 ent = bcma_erom_get_ent(bus, eromptr);
|
|
bcma_erom_push_ent(eromptr);
|
|
return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
|
|
}
|
|
|
|
-static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
|
|
+static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
|
|
{
|
|
u32 ent = bcma_erom_get_ent(bus, eromptr);
|
|
bcma_erom_push_ent(eromptr);
|
|
@@ -175,7 +177,7 @@ static bool bcma_erom_is_bridge(struct b
|
|
((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
|
|
}
|
|
|
|
-static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
|
|
+static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
|
|
{
|
|
u32 ent;
|
|
while (1) {
|
|
@@ -189,7 +191,7 @@ static void bcma_erom_skip_component(str
|
|
bcma_erom_push_ent(eromptr);
|
|
}
|
|
|
|
-static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
|
|
+static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
|
|
{
|
|
u32 ent = bcma_erom_get_ent(bus, eromptr);
|
|
if (!(ent & SCAN_ER_VALID))
|
|
@@ -199,7 +201,7 @@ static s32 bcma_erom_get_mst_port(struct
|
|
return ent;
|
|
}
|
|
|
|
-static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
|
|
+static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
|
|
u32 type, u8 port)
|
|
{
|
|
u32 addrl, addrh, sizel, sizeh = 0;
|
|
--- a/drivers/bcma/sprom.c
|
|
+++ b/drivers/bcma/sprom.c
|
|
@@ -72,12 +72,12 @@ fail:
|
|
* R/W ops.
|
|
**************************************************/
|
|
|
|
-static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
|
|
+static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
|
|
+ size_t words)
|
|
{
|
|
int i;
|
|
- for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
|
|
- sprom[i] = bcma_read16(bus->drv_cc.core,
|
|
- offset + (i * 2));
|
|
+ for (i = 0; i < words; i++)
|
|
+ sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
|
|
}
|
|
|
|
/**************************************************
|
|
@@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
|
|
return t[crc ^ data];
|
|
}
|
|
|
|
-static u8 bcma_sprom_crc(const u16 *sprom)
|
|
+static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
|
|
{
|
|
int word;
|
|
u8 crc = 0xFF;
|
|
|
|
- for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
|
|
+ for (word = 0; word < words - 1; word++) {
|
|
crc = bcma_crc8(crc, sprom[word] & 0x00FF);
|
|
crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
|
|
}
|
|
- crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
|
|
+ crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
|
|
crc ^= 0xFF;
|
|
|
|
return crc;
|
|
}
|
|
|
|
-static int bcma_sprom_check_crc(const u16 *sprom)
|
|
+static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
|
|
{
|
|
u8 crc;
|
|
u8 expected_crc;
|
|
u16 tmp;
|
|
|
|
- crc = bcma_sprom_crc(sprom);
|
|
- tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
|
|
+ crc = bcma_sprom_crc(sprom, words);
|
|
+ tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
|
|
expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
|
|
if (crc != expected_crc)
|
|
return -EPROTO;
|
|
@@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
|
|
return 0;
|
|
}
|
|
|
|
-static int bcma_sprom_valid(const u16 *sprom)
|
|
+static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
|
|
+ size_t words)
|
|
{
|
|
u16 revision;
|
|
int err;
|
|
|
|
- err = bcma_sprom_check_crc(sprom);
|
|
+ err = bcma_sprom_check_crc(sprom, words);
|
|
if (err)
|
|
return err;
|
|
|
|
- revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
|
|
- if (revision != 8 && revision != 9) {
|
|
+ revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
|
|
+ if (revision != 8 && revision != 9 && revision != 10) {
|
|
pr_err("Unsupported SPROM revision: %d\n", revision);
|
|
return -ENOENT;
|
|
}
|
|
|
|
+ bus->sprom.revision = revision;
|
|
+ bcma_debug(bus, "Found SPROM revision %d\n", revision);
|
|
+
|
|
return 0;
|
|
}
|
|
|
|
@@ -208,15 +212,13 @@ static void bcma_sprom_extract_r8(struct
|
|
BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
|
|
ARRAY_SIZE(bus->sprom.core_pwr_info));
|
|
|
|
- bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
|
|
- SSB_SPROM_REVISION_REV;
|
|
-
|
|
for (i = 0; i < 3; i++) {
|
|
v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
|
|
*(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
|
|
}
|
|
|
|
SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
|
|
+ SPEX(board_type, SSB_SPROM1_SPID, ~0, 0);
|
|
|
|
SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
|
|
SSB_SPROM4_TXPID2G0_SHIFT);
|
|
@@ -501,13 +503,15 @@ static bool bcma_sprom_onchip_available(
|
|
case BCMA_CHIP_ID_BCM4331:
|
|
present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
|
|
break;
|
|
-
|
|
+ case BCMA_CHIP_ID_BCM43142:
|
|
case BCMA_CHIP_ID_BCM43224:
|
|
case BCMA_CHIP_ID_BCM43225:
|
|
/* for these chips OTP is always available */
|
|
present = true;
|
|
break;
|
|
+ case BCMA_CHIP_ID_BCM43227:
|
|
case BCMA_CHIP_ID_BCM43228:
|
|
+ case BCMA_CHIP_ID_BCM43428:
|
|
present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
|
|
break;
|
|
default:
|
|
@@ -547,7 +551,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
|
|
{
|
|
u16 offset = BCMA_CC_SPROM;
|
|
u16 *sprom;
|
|
- int err = 0;
|
|
+ size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
|
|
+ SSB_SPROMSIZE_WORDS_R10, };
|
|
+ int i, err = 0;
|
|
|
|
if (!bus->drv_cc.core)
|
|
return -EOPNOTSUPP;
|
|
@@ -576,29 +582,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
|
|
}
|
|
}
|
|
|
|
- sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
|
|
- GFP_KERNEL);
|
|
- if (!sprom)
|
|
- return -ENOMEM;
|
|
-
|
|
if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
|
|
bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
|
|
bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
|
|
|
|
bcma_debug(bus, "SPROM offset 0x%x\n", offset);
|
|
- bcma_sprom_read(bus, offset, sprom);
|
|
+ for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
|
|
+ size_t words = sprom_sizes[i];
|
|
+
|
|
+ sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
|
|
+ if (!sprom)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ bcma_sprom_read(bus, offset, sprom, words);
|
|
+ err = bcma_sprom_valid(bus, sprom, words);
|
|
+ if (!err)
|
|
+ break;
|
|
+
|
|
+ kfree(sprom);
|
|
+ }
|
|
|
|
if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
|
|
bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
|
|
bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
|
|
|
|
- err = bcma_sprom_valid(sprom);
|
|
- if (err)
|
|
- goto out;
|
|
-
|
|
- bcma_sprom_extract_r8(bus, sprom);
|
|
+ if (err) {
|
|
+ bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
|
|
+ err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
|
|
+ } else {
|
|
+ bcma_sprom_extract_r8(bus, sprom);
|
|
+ kfree(sprom);
|
|
+ }
|
|
|
|
-out:
|
|
- kfree(sprom);
|
|
return err;
|
|
}
|
|
--- a/include/linux/bcma/bcma.h
|
|
+++ b/include/linux/bcma/bcma.h
|
|
@@ -10,7 +10,7 @@
|
|
#include <linux/bcma/bcma_driver_gmac_cmn.h>
|
|
#include <linux/ssb/ssb.h> /* SPROM sharing */
|
|
|
|
-#include "bcma_regs.h"
|
|
+#include <linux/bcma/bcma_regs.h>
|
|
|
|
struct bcma_device;
|
|
struct bcma_bus;
|
|
@@ -134,12 +134,17 @@ struct bcma_host_ops {
|
|
#define BCMA_CORE_I2S 0x834
|
|
#define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
|
|
#define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
|
|
+#define BCMA_CORE_PHY_AC 0x83B
|
|
+#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
|
|
+#define BCMA_CORE_USB30_DEV 0x83D
|
|
+#define BCMA_CORE_ARM_CR4 0x83E
|
|
#define BCMA_CORE_DEFAULT 0xFFF
|
|
|
|
#define BCMA_MAX_NR_CORES 16
|
|
|
|
/* Chip IDs of PCIe devices */
|
|
#define BCMA_CHIP_ID_BCM4313 0x4313
|
|
+#define BCMA_CHIP_ID_BCM43142 43142
|
|
#define BCMA_CHIP_ID_BCM43224 43224
|
|
#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
|
|
#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
|
|
@@ -157,6 +162,7 @@ struct bcma_host_ops {
|
|
|
|
/* Chip IDs of SoCs */
|
|
#define BCMA_CHIP_ID_BCM4706 0x5300
|
|
+#define BCMA_PKG_ID_BCM4706L 1
|
|
#define BCMA_CHIP_ID_BCM4716 0x4716
|
|
#define BCMA_PKG_ID_BCM4716 8
|
|
#define BCMA_PKG_ID_BCM4717 9
|
|
@@ -166,7 +172,65 @@ struct bcma_host_ops {
|
|
#define BCMA_CHIP_ID_BCM4749 0x4749
|
|
#define BCMA_CHIP_ID_BCM5356 0x5356
|
|
#define BCMA_CHIP_ID_BCM5357 0x5357
|
|
+#define BCMA_PKG_ID_BCM5358 9
|
|
+#define BCMA_PKG_ID_BCM47186 10
|
|
+#define BCMA_PKG_ID_BCM5357 11
|
|
#define BCMA_CHIP_ID_BCM53572 53572
|
|
+#define BCMA_PKG_ID_BCM47188 9
|
|
+
|
|
+/* Board types (on PCI usually equals to the subsystem dev id) */
|
|
+/* BCM4313 */
|
|
+#define BCMA_BOARD_TYPE_BCM94313BU 0X050F
|
|
+#define BCMA_BOARD_TYPE_BCM94313HM 0X0510
|
|
+#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511
|
|
+#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C
|
|
+/* BCM4716 */
|
|
+#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD
|
|
+/* BCM43224 */
|
|
+#define BCMA_BOARD_TYPE_BCM943224X21 0X056E
|
|
+#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1
|
|
+#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9
|
|
+#define BCMA_BOARD_TYPE_BCM943224M93 0X008B
|
|
+#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090
|
|
+#define BCMA_BOARD_TYPE_BCM943224X16 0X0093
|
|
+#define BCMA_BOARD_TYPE_BCM94322X9 0X008D
|
|
+#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E
|
|
+/* BCM43228 */
|
|
+#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540
|
|
+#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541
|
|
+#define BCMA_BOARD_TYPE_BCM943228BU 0X0542
|
|
+#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543
|
|
+#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544
|
|
+#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545
|
|
+#define BCMA_BOARD_TYPE_BCM943228SD 0X0573
|
|
+/* BCM4331 */
|
|
+#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6
|
|
+#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4
|
|
+#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E
|
|
+#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4
|
|
+#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC
|
|
+#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED
|
|
+#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF
|
|
+#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF
|
|
+#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5
|
|
+#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4
|
|
+#define BCMA_BOARD_TYPE_BCM94331BU 0X0523
|
|
+#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524
|
|
+#define BCMA_BOARD_TYPE_BCM94331MC 0X0525
|
|
+#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526
|
|
+#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527
|
|
+#define BCMA_BOARD_TYPE_BCM94331HM 0X0574
|
|
+#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B
|
|
+#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9
|
|
+#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6
|
|
+#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA
|
|
+/* BCM53572 */
|
|
+#define BCMA_BOARD_TYPE_BCM953572BU 0X058D
|
|
+#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E
|
|
+#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F
|
|
+#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590
|
|
+/* BCM43142 */
|
|
+#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0
|
|
|
|
struct bcma_device {
|
|
struct bcma_bus *bus;
|
|
@@ -251,7 +315,7 @@ struct bcma_bus {
|
|
u8 num;
|
|
|
|
struct bcma_drv_cc drv_cc;
|
|
- struct bcma_drv_pci drv_pci;
|
|
+ struct bcma_drv_pci drv_pci[2];
|
|
struct bcma_drv_mips drv_mips;
|
|
struct bcma_drv_gmac_cmn drv_gmac_cmn;
|
|
|
|
@@ -345,6 +409,7 @@ extern void bcma_core_set_clockmode(stru
|
|
enum bcma_clkmode clkmode);
|
|
extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
|
|
bool on);
|
|
+extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
|
|
#define BCMA_DMA_TRANSLATION_MASK 0xC0000000
|
|
#define BCMA_DMA_TRANSLATION_NONE 0x00000000
|
|
#define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
|
|
--- a/include/linux/bcma/bcma_driver_chipcommon.h
|
|
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
|
|
@@ -1,6 +1,9 @@
|
|
#ifndef LINUX_BCMA_DRIVER_CC_H_
|
|
#define LINUX_BCMA_DRIVER_CC_H_
|
|
|
|
+#include <linux/platform_device.h>
|
|
+#include <linux/gpio.h>
|
|
+
|
|
/** ChipCommon core registers. **/
|
|
#define BCMA_CC_ID 0x0000
|
|
#define BCMA_CC_ID_ID 0x0000FFFF
|
|
@@ -24,7 +27,7 @@
|
|
#define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
|
|
#define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
|
|
#define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
|
|
-#define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */
|
|
+#define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */
|
|
#define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
|
|
#define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
|
|
#define BCMA_PLLTYPE_NONE 0x00000000
|
|
@@ -100,6 +103,8 @@
|
|
#define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
|
|
#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
|
|
#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
|
|
+#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
|
|
+#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
|
|
#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
|
|
#define BCMA_CC_JCMD_START 0x80000000
|
|
#define BCMA_CC_JCMD_BUSY 0x80000000
|
|
@@ -266,6 +271,29 @@
|
|
#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
|
|
#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
|
|
#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
|
|
+/* Block 0x140 - 0x190 registers are chipset specific */
|
|
+#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
|
|
+#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
|
|
+#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
|
|
+#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
|
|
+#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
|
|
+#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
|
|
+/* NAND flash registers for BCM4706 (corerev = 31) */
|
|
+#define BCMA_CC_NFLASH_CTL 0x01A0
|
|
+#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
|
|
+#define BCMA_CC_NFLASH_CONF 0x01A4
|
|
+#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
|
|
+#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
|
|
+#define BCMA_CC_NFLASH_DATA 0x01B0
|
|
+#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
|
|
/* 0x1E0 is defined as shared BCMA_CLKCTLST */
|
|
#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
|
|
#define BCMA_CC_UART0_DATA 0x0300
|
|
@@ -288,6 +316,9 @@
|
|
#define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
|
|
#define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
|
|
#define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
|
|
+#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
|
|
+#define BCMA_CC_PMU_CTL_RES_SHIFT 13
|
|
+#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
|
|
#define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
|
|
#define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
|
|
#define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
|
|
@@ -299,6 +330,8 @@
|
|
#define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
|
|
#define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
|
|
#define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
|
|
+#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
|
|
+#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
|
|
#define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
|
|
#define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
|
|
#define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
|
|
@@ -324,7 +357,66 @@
|
|
#define BCMA_CC_REGCTL_DATA 0x065C
|
|
#define BCMA_CC_PLLCTL_ADDR 0x0660
|
|
#define BCMA_CC_PLLCTL_DATA 0x0664
|
|
+#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
|
|
+#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
|
|
+#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
|
|
+#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
|
|
+#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
|
|
#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
|
|
+/* NAND flash MLC controller registers (corerev >= 38) */
|
|
+#define BCMA_CC_NAND_REVISION 0x0C00
|
|
+#define BCMA_CC_NAND_CMD_START 0x0C04
|
|
+#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
|
|
+#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
|
|
+#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
|
|
+#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
|
|
+#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
|
|
+#define BCMA_CC_NAND_SPARE_RD0 0x0C20
|
|
+#define BCMA_CC_NAND_SPARE_RD4 0x0C24
|
|
+#define BCMA_CC_NAND_SPARE_RD8 0x0C28
|
|
+#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
|
|
+#define BCMA_CC_NAND_SPARE_WR0 0x0C30
|
|
+#define BCMA_CC_NAND_SPARE_WR4 0x0C34
|
|
+#define BCMA_CC_NAND_SPARE_WR8 0x0C38
|
|
+#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
|
|
+#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
|
|
+#define BCMA_CC_NAND_CONFIG 0x0C48
|
|
+#define BCMA_CC_NAND_TIMING_1 0x0C50
|
|
+#define BCMA_CC_NAND_TIMING_2 0x0C54
|
|
+#define BCMA_CC_NAND_SEMAPHORE 0x0C58
|
|
+#define BCMA_CC_NAND_DEVID 0x0C60
|
|
+#define BCMA_CC_NAND_DEVID_X 0x0C64
|
|
+#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
|
|
+#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
|
|
+#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
|
|
+#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
|
|
+#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
|
|
+#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
|
|
+#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
|
|
+#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
|
|
+#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
|
|
+#define BCMA_CC_NAND_READ_ADDR 0x0C94
|
|
+#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
|
|
+#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
|
|
+#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
|
|
+#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
|
|
+#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
|
|
+#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
|
|
+#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
|
|
+#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
|
|
+#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
|
|
+#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
|
|
+#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
|
|
+#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
|
|
+#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
|
|
+#define BCMA_CC_NAND_SPARE_RD16 0x0D30
|
|
+#define BCMA_CC_NAND_SPARE_RD20 0x0D34
|
|
+#define BCMA_CC_NAND_SPARE_RD24 0x0D38
|
|
+#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
|
|
+#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
|
|
+#define BCMA_CC_NAND_CACHE_DATA 0x0D44
|
|
+#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
|
|
+#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
|
|
|
|
/* Divider allocation in 4716/47162/5356 */
|
|
#define BCMA_CC_PMU5_MAINPLL_CPU 1
|
|
@@ -350,6 +442,23 @@
|
|
#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
|
|
#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
|
|
|
|
+/* PMU rev 15 */
|
|
+#define BCMA_CC_PMU15_PLL_PLLCTL0 0
|
|
+#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
|
|
+#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
|
|
+#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
|
|
+#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
|
|
+#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
|
|
+#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
|
|
+#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
|
|
+#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
|
|
+#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
|
|
+#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
|
|
+#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
|
|
+#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
|
|
+#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
|
|
+#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
|
|
+
|
|
/* ALP clock on pre-PMU chips */
|
|
#define BCMA_CC_PMU_ALP_CLOCK 20000000
|
|
/* HT clock for systems with PMU-enabled chipcommon */
|
|
@@ -415,6 +524,44 @@
|
|
/* 4313 Chip specific ChipControl register bits */
|
|
#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
|
|
|
|
+/* BCM5357 ChipControl register bits */
|
|
+#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
|
|
+#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
|
|
+#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
|
|
+#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
|
|
+#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
|
|
+
|
|
+#define BCMA_RES_4314_LPLDO_PU BIT(0)
|
|
+#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
|
|
+#define BCMA_RES_4314_PMU_BG_PU BIT(2)
|
|
+#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
|
|
+#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
|
|
+#define BCMA_RES_4314_CLDO_PU BIT(5)
|
|
+#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
|
|
+#define BCMA_RES_4314_WL_PMU_PU BIT(7)
|
|
+#define BCMA_RES_4314_LNLDO_PU BIT(8)
|
|
+#define BCMA_RES_4314_LDO3P3_PU BIT(9)
|
|
+#define BCMA_RES_4314_OTP_PU BIT(10)
|
|
+#define BCMA_RES_4314_XTAL_PU BIT(11)
|
|
+#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
|
|
+#define BCMA_RES_4314_LQ_AVAIL BIT(13)
|
|
+#define BCMA_RES_4314_LOGIC_RET BIT(14)
|
|
+#define BCMA_RES_4314_MEM_SLEEP BIT(15)
|
|
+#define BCMA_RES_4314_MACPHY_RET BIT(16)
|
|
+#define BCMA_RES_4314_WL_CORE_READY BIT(17)
|
|
+#define BCMA_RES_4314_ILP_REQ BIT(18)
|
|
+#define BCMA_RES_4314_ALP_AVAIL BIT(19)
|
|
+#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
|
|
+#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
|
|
+#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
|
|
+#define BCMA_RES_4314_RADIO_PU BIT(23)
|
|
+#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
|
|
+#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
|
|
+#define BCMA_RES_4314_RX_LDO_PU BIT(26)
|
|
+#define BCMA_RES_4314_TX_LDO_PU BIT(27)
|
|
+#define BCMA_RES_4314_HT_AVAIL BIT(28)
|
|
+#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
|
|
+
|
|
/* Data for the PMU, if available.
|
|
* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
|
|
*/
|
|
@@ -425,11 +572,36 @@ struct bcma_chipcommon_pmu {
|
|
|
|
#ifdef CONFIG_BCMA_DRIVER_MIPS
|
|
struct bcma_pflash {
|
|
+ bool present;
|
|
u8 buswidth;
|
|
u32 window;
|
|
u32 window_size;
|
|
};
|
|
|
|
+#ifdef CONFIG_BCMA_SFLASH
|
|
+struct bcma_sflash {
|
|
+ bool present;
|
|
+ u32 window;
|
|
+ u32 blocksize;
|
|
+ u16 numblocks;
|
|
+ u32 size;
|
|
+
|
|
+ struct mtd_info *mtd;
|
|
+ void *priv;
|
|
+};
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_BCMA_NFLASH
|
|
+struct mtd_info;
|
|
+
|
|
+struct bcma_nflash {
|
|
+ bool present;
|
|
+ bool boot; /* This is the flash the SoC boots from */
|
|
+
|
|
+ struct mtd_info *mtd;
|
|
+};
|
|
+#endif
|
|
+
|
|
struct bcma_serial_port {
|
|
void *regs;
|
|
unsigned long clockspeed;
|
|
@@ -445,15 +617,30 @@ struct bcma_drv_cc {
|
|
u32 capabilities;
|
|
u32 capabilities_ext;
|
|
u8 setup_done:1;
|
|
+ u8 early_setup_done:1;
|
|
/* Fast Powerup Delay constant */
|
|
u16 fast_pwrup_delay;
|
|
struct bcma_chipcommon_pmu pmu;
|
|
#ifdef CONFIG_BCMA_DRIVER_MIPS
|
|
struct bcma_pflash pflash;
|
|
+#ifdef CONFIG_BCMA_SFLASH
|
|
+ struct bcma_sflash sflash;
|
|
+#endif
|
|
+#ifdef CONFIG_BCMA_NFLASH
|
|
+ struct bcma_nflash nflash;
|
|
+#endif
|
|
|
|
int nr_serial_ports;
|
|
struct bcma_serial_port serial_ports[4];
|
|
#endif /* CONFIG_BCMA_DRIVER_MIPS */
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+ u32 ticks_per_ms;
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+ struct platform_device *watchdog;
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+
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+ /* Lock for GPIO register access. */
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+ spinlock_t gpio_lock;
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+#ifdef CONFIG_BCMA_DRIVER_GPIO
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+ struct gpio_chip gpio;
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+#endif
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};
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/* Register access */
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@@ -470,14 +657,16 @@ struct bcma_drv_cc {
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bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
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|
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extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
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+extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
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|
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extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
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extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
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|
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void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
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|
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-extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
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- u32 ticks);
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+extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
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+
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+extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
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|
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void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
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|
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@@ -490,9 +679,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
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u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
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u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
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u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
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+u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
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+u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
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|
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/* PMU support */
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extern void bcma_pmu_init(struct bcma_drv_cc *cc);
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+extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
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|
|
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extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
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u32 value);
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@@ -504,4 +696,6 @@ extern void bcma_chipco_regctl_maskset(s
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u32 offset, u32 mask, u32 set);
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extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
|
|
|
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+extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
|
|
+
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#endif /* LINUX_BCMA_DRIVER_CC_H_ */
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--- a/include/linux/bcma/bcma_driver_mips.h
|
|
+++ b/include/linux/bcma/bcma_driver_mips.h
|
|
@@ -28,6 +28,7 @@
|
|
#define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
|
|
#define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
|
|
|
|
+#define BCMA_MIPS_OOBSELINA74 0x004
|
|
#define BCMA_MIPS_OOBSELOUTA30 0x100
|
|
|
|
struct bcma_device;
|
|
@@ -35,17 +36,24 @@ struct bcma_device;
|
|
struct bcma_drv_mips {
|
|
struct bcma_device *core;
|
|
u8 setup_done:1;
|
|
- unsigned int assigned_irqs;
|
|
+ u8 early_setup_done:1;
|
|
};
|
|
|
|
#ifdef CONFIG_BCMA_DRIVER_MIPS
|
|
extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
|
|
+extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
|
|
+
|
|
+extern unsigned int bcma_core_irq(struct bcma_device *core);
|
|
#else
|
|
static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
|
|
+static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
|
|
+
|
|
+static inline unsigned int bcma_core_irq(struct bcma_device *core)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
#endif
|
|
|
|
extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
|
|
|
|
-extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
|
|
-
|
|
#endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
|
|
--- a/include/linux/bcma/bcma_driver_pci.h
|
|
+++ b/include/linux/bcma/bcma_driver_pci.h
|
|
@@ -179,6 +179,8 @@ struct pci_dev;
|
|
#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
|
|
#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
|
|
|
|
+#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
|
|
+
|
|
/* PCIE Root Capability Register bits (Host mode only) */
|
|
#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
|
|
|
|
--- a/include/linux/bcma/bcma_regs.h
|
|
+++ b/include/linux/bcma/bcma_regs.h
|
|
@@ -11,11 +11,13 @@
|
|
#define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
|
|
#define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
|
|
#define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
|
|
+#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
|
|
#define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
|
|
#define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
|
|
#define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
|
|
#define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
|
|
#define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
|
|
+#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
|
|
/* Is there any BCM4328 on BCMA bus? */
|
|
#define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
|
|
#define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
|
|
@@ -35,6 +37,7 @@
|
|
#define BCMA_IOST_BIST_DONE 0x8000
|
|
#define BCMA_RESET_CTL 0x0800
|
|
#define BCMA_RESET_CTL_RESET 0x0001
|
|
+#define BCMA_RESET_ST 0x0804
|
|
|
|
/* BCMA PCI config space registers. */
|
|
#define BCMA_PCI_PMCSR 0x44
|
|
@@ -83,4 +86,9 @@
|
|
* (2 ZettaBytes), high 32 bits
|
|
*/
|
|
|
|
+#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
|
|
+#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
|
|
+#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
|
|
+#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
|
|
+
|
|
#endif /* LINUX_BCMA_REGS_H_ */
|
|
--- a/drivers/net/wireless/b43/main.c
|
|
+++ b/drivers/net/wireless/b43/main.c
|
|
@@ -4622,7 +4622,7 @@ static int b43_wireless_core_init(struct
|
|
switch (dev->dev->bus_type) {
|
|
#ifdef CONFIG_B43_BCMA
|
|
case B43_BUS_BCMA:
|
|
- bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
|
|
+ bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
|
|
dev->dev->bdev, true);
|
|
break;
|
|
#endif
|
|
--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
|
|
+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
|
|
@@ -695,7 +695,7 @@ void ai_pci_up(struct si_pub *sih)
|
|
sii = container_of(sih, struct si_info, pub);
|
|
|
|
if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
|
|
- bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
|
|
+ bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
|
|
}
|
|
|
|
/* Unconfigure and/or apply various WARs when going down */
|
|
@@ -706,7 +706,7 @@ void ai_pci_down(struct si_pub *sih)
|
|
sii = container_of(sih, struct si_info, pub);
|
|
|
|
if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
|
|
- bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
|
|
+ bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
|
|
}
|
|
|
|
/* Enable BT-COEX & Ex-PA for 4313 */
|
|
--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
|
|
+++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
|
|
@@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
|
|
* Configure pci/pcmcia here instead of in brcms_c_attach()
|
|
* to allow mfg hotswap: down, hotswap (chip power cycle), up.
|
|
*/
|
|
- bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
|
|
+ bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
|
|
true);
|
|
|
|
/*
|