mirror of https://github.com/hak5/openwrt-owl.git
636 lines
18 KiB
Diff
636 lines
18 KiB
Diff
From a0ad1511d5805b95ac4c454d7904c670a1696055 Mon Sep 17 00:00:00 2001
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From: Kapil Hali <kapilh@broadcom.com>
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Date: Wed, 14 Oct 2015 13:47:00 -0400
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Subject: [PATCH] ARM: BCM: Add SMP support for Broadcom NSP
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Add SMP support for Broadcom's Northstar Plus SoC,
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cpu enable method and pen_release procedures. This
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changes also consolidates iProc family's - BCM NSP
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and BCM Kona, SMP handling in a common file.
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Northstar Plus SoC is based on ARM Cortex-A9
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revision r3p0 which requires configuration for ARM
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Errata 764369 for SMP. This change adds the needed
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configuration option.
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Signed-off-by: Kapil Hali <kapilh@broadcom.com>
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---
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arch/arm/mach-bcm/Makefile | 2 +-
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arch/arm/mach-bcm/bcm_nsp.h | 19 +++
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arch/arm/mach-bcm/headsmp.S | 37 +++++
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arch/arm/mach-bcm/kona_smp.c | 202 ---------------------------
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arch/arm/mach-bcm/platsmp.c | 326 +++++++++++++++++++++++++++++++++++++++++++
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5 files changed, 383 insertions(+), 203 deletions(-)
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create mode 100644 arch/arm/mach-bcm/bcm_nsp.h
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create mode 100644 arch/arm/mach-bcm/headsmp.S
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delete mode 100644 arch/arm/mach-bcm/kona_smp.c
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create mode 100644 arch/arm/mach-bcm/platsmp.c
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--- a/arch/arm/mach-bcm/Makefile
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+++ b/arch/arm/mach-bcm/Makefile
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@@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bc
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obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o
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# BCM281XX and BCM21664 SMP support
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-obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o
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+obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o
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# BCM281XX and BCM21664 L2 cache control
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obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
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--- /dev/null
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+++ b/arch/arm/mach-bcm/bcm_nsp.h
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@@ -0,0 +1,19 @@
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+/*
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+ * Copyright (C) 2015 Broadcom Corporation
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation version 2.
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+ *
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+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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+ * kind, whether express or implied; without even the implied warranty
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+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#ifndef __BCM_NSP_H
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+#define __BCM_NSP_H
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+
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+extern void nsp_secondary_startup(void);
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+
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+#endif /* __BCM_NSP_H */
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--- /dev/null
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+++ b/arch/arm/mach-bcm/headsmp.S
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@@ -0,0 +1,37 @@
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+/*
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+ * Copyright (C) 2015 Broadcom Corporation
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation version 2.
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+ *
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+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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+ * kind, whether express or implied; without even the implied warranty
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+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/linkage.h>
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+
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+/*
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+ * iProc specific entry point for secondary CPUs. This provides
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+ * a "holding pen" into which all secondary cores are held until
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+ * we are ready for them to initialise.
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+ */
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+ENTRY(nsp_secondary_startup)
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+ mrc p15, 0, r0, c0, c0, 5
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+ and r0, r0, #15
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+ adr r4, 1f
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+ ldmia r4, {r5, r6}
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+ sub r4, r4, r5
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+ add r6, r6, r4
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+pen: ldr r7, [r6]
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+ cmp r7, r0
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+ bne pen
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+
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+ b secondary_startup
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+
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+1: .long .
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+ .long pen_release
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+
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+ENDPROC(nsp_secondary_startup)
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--- a/arch/arm/mach-bcm/kona_smp.c
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+++ /dev/null
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@@ -1,202 +0,0 @@
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-/*
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- * Copyright (C) 2014 Broadcom Corporation
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- * Copyright 2014 Linaro Limited
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License as
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- * published by the Free Software Foundation version 2.
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- *
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- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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- * kind, whether express or implied; without even the implied warranty
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- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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- */
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-
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-#include <linux/init.h>
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-#include <linux/errno.h>
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-#include <linux/io.h>
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-#include <linux/of.h>
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-#include <linux/sched.h>
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-
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-#include <asm/smp.h>
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-#include <asm/smp_plat.h>
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-#include <asm/smp_scu.h>
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-
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-/* Size of mapped Cortex A9 SCU address space */
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-#define CORTEX_A9_SCU_SIZE 0x58
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-
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-#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */
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-#define BOOT_ADDR_CPUID_MASK 0x3
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-
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-/* Name of device node property defining secondary boot register location */
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-#define OF_SECONDARY_BOOT "secondary-boot-reg"
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-
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-/* I/O address of register used to coordinate secondary core startup */
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-static u32 secondary_boot;
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-
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-/*
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- * Enable the Cortex A9 Snoop Control Unit
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- *
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- * By the time this is called we already know there are multiple
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- * cores present. We assume we're running on a Cortex A9 processor,
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- * so any trouble getting the base address register or getting the
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- * SCU base is a problem.
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- *
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- * Return 0 if successful or an error code otherwise.
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- */
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-static int __init scu_a9_enable(void)
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-{
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- unsigned long config_base;
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- void __iomem *scu_base;
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-
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- if (!scu_a9_has_base()) {
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- pr_err("no configuration base address register!\n");
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- return -ENXIO;
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- }
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-
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- /* Config base address register value is zero for uniprocessor */
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- config_base = scu_a9_get_base();
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- if (!config_base) {
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- pr_err("hardware reports only one core\n");
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- return -ENOENT;
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- }
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-
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- scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
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- if (!scu_base) {
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- pr_err("failed to remap config base (%lu/%u) for SCU\n",
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- config_base, CORTEX_A9_SCU_SIZE);
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- return -ENOMEM;
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- }
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-
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- scu_enable(scu_base);
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-
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- iounmap(scu_base); /* That's the last we'll need of this */
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-
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- return 0;
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-}
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-
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-static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
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-{
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- static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
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- struct device_node *node;
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- int ret;
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-
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- BUG_ON(secondary_boot); /* We're called only once */
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-
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- /*
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- * This function is only called via smp_ops->smp_prepare_cpu().
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- * That only happens if a "/cpus" device tree node exists
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- * and has an "enable-method" property that selects the SMP
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- * operations defined herein.
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- */
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- node = of_find_node_by_path("/cpus");
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- BUG_ON(!node);
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-
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- /*
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- * Our secondary enable method requires a "secondary-boot-reg"
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- * property to specify a register address used to request the
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- * ROM code boot a secondary code. If we have any trouble
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- * getting this we fall back to uniprocessor mode.
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- */
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- if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
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- pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
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- node->name);
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- ret = -ENOENT; /* Arrange to disable SMP */
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- goto out;
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- }
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-
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- /*
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- * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
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- * returned, the SoC reported a uniprocessor configuration.
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- * We bail on any other error.
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- */
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- ret = scu_a9_enable();
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-out:
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- of_node_put(node);
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- if (ret) {
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- /* Update the CPU present map to reflect uniprocessor mode */
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- BUG_ON(ret != -ENOENT);
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- pr_warn("disabling SMP\n");
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- init_cpu_present(&only_cpu_0);
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- }
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-}
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-
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-/*
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- * The ROM code has the secondary cores looping, waiting for an event.
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- * When an event occurs each core examines the bottom two bits of the
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- * secondary boot register. When a core finds those bits contain its
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- * own core id, it performs initialization, including computing its boot
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- * address by clearing the boot register value's bottom two bits. The
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- * core signals that it is beginning its execution by writing its boot
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- * address back to the secondary boot register, and finally jumps to
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- * that address.
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- *
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- * So to start a core executing we need to:
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- * - Encode the (hardware) CPU id with the bottom bits of the secondary
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- * start address.
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- * - Write that value into the secondary boot register.
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- * - Generate an event to wake up the secondary CPU(s).
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- * - Wait for the secondary boot register to be re-written, which
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- * indicates the secondary core has started.
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- */
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-static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
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-{
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- void __iomem *boot_reg;
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- phys_addr_t boot_func;
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- u64 start_clock;
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- u32 cpu_id;
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- u32 boot_val;
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- bool timeout = false;
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-
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- cpu_id = cpu_logical_map(cpu);
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- if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
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- pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
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- return -EINVAL;
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- }
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-
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- if (!secondary_boot) {
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- pr_err("required secondary boot register not specified\n");
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- return -EINVAL;
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- }
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-
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- boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32));
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- if (!boot_reg) {
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- pr_err("unable to map boot register for cpu %u\n", cpu_id);
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- return -ENOSYS;
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- }
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-
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- /*
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- * Secondary cores will start in secondary_startup(),
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- * defined in "arch/arm/kernel/head.S"
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- */
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- boot_func = virt_to_phys(secondary_startup);
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- BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
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- BUG_ON(boot_func > (phys_addr_t)U32_MAX);
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-
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- /* The core to start is encoded in the low bits */
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- boot_val = (u32)boot_func | cpu_id;
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- writel_relaxed(boot_val, boot_reg);
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-
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- sev();
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-
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- /* The low bits will be cleared once the core has started */
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- start_clock = local_clock();
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- while (!timeout && readl_relaxed(boot_reg) == boot_val)
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- timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;
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-
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- iounmap(boot_reg);
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-
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- if (!timeout)
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- return 0;
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-
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- pr_err("timeout waiting for cpu %u to start\n", cpu_id);
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-
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- return -ENOSYS;
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-}
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-
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-static struct smp_operations bcm_smp_ops __initdata = {
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- .smp_prepare_cpus = bcm_smp_prepare_cpus,
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- .smp_boot_secondary = bcm_boot_secondary,
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-};
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-CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
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- &bcm_smp_ops);
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--- /dev/null
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+++ b/arch/arm/mach-bcm/platsmp.c
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@@ -0,0 +1,326 @@
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+/*
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+ * Copyright (C) 2014-2015 Broadcom Corporation
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+ * Copyright 2014 Linaro Limited
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation version 2.
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+ *
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+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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+ * kind, whether express or implied; without even the implied warranty
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+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/cpumask.h>
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+#include <linux/delay.h>
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+#include <linux/errno.h>
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+#include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/jiffies.h>
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+#include <linux/of.h>
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+#include <linux/sched.h>
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+#include <linux/smp.h>
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+
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+#include <asm/cacheflush.h>
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+#include <asm/smp.h>
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+#include <asm/smp_plat.h>
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+#include <asm/smp_scu.h>
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+
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+#include "bcm_nsp.h"
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+
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+/* Size of mapped Cortex A9 SCU address space */
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+#define CORTEX_A9_SCU_SIZE 0x58
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+
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+#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */
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+#define BOOT_ADDR_CPUID_MASK 0x3
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+
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+/* Name of device node property defining secondary boot register location */
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+#define OF_SECONDARY_BOOT "secondary-boot-reg"
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+
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+/* I/O address of register used to coordinate secondary core startup */
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+static u32 secondary_boot;
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+
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+static DEFINE_SPINLOCK(boot_lock);
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+
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+/*
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+ * Write pen_release in a way that is guaranteed to be visible to all
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+ * observers, irrespective of whether they're taking part in coherency
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+ * or not. This is necessary for the hotplug code to work reliably.
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+ */
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+static void write_pen_release(int val)
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+{
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+ pen_release = val;
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+ /*
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+ * Ensure write to pen_release is visible to the other cores,
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+ * here - primary core
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+ */
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+ smp_wmb();
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+ sync_cache_w(&pen_release);
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+}
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+
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+/*
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+ * Enable the Cortex A9 Snoop Control Unit
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+ *
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+ * By the time this is called we already know there are multiple
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+ * cores present. We assume we're running on a Cortex A9 processor,
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+ * so any trouble getting the base address register or getting the
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+ * SCU base is a problem.
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+ *
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+ * Return 0 if successful or an error code otherwise.
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+ */
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+static int __init scu_a9_enable(void)
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+{
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+ unsigned long config_base;
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+ void __iomem *scu_base;
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+
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+ if (!scu_a9_has_base()) {
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+ pr_err("no configuration base address register!\n");
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+ return -ENXIO;
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+ }
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+
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+ /* Config base address register value is zero for uniprocessor */
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+ config_base = scu_a9_get_base();
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+ if (!config_base) {
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+ pr_err("hardware reports only one core\n");
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+ return -ENOENT;
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+ }
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+
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+ scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
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+ if (!scu_base) {
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+ pr_err("failed to remap config base (%lu/%u) for SCU\n",
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+ config_base, CORTEX_A9_SCU_SIZE);
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+ return -ENOMEM;
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+ }
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+
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+ scu_enable(scu_base);
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+
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+ iounmap(scu_base); /* That's the last we'll need of this */
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+
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+ return 0;
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+}
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+
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+static int nsp_write_lut(void (*secondary_startup) (void))
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+{
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+ void __iomem *sku_rom_lut;
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+ phys_addr_t secondary_startup_phy;
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+
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+ if (!secondary_boot) {
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+ pr_warn("required secondary boot register not specified\n");
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+ return -EINVAL;
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+ }
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+
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+ sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot,
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+ sizeof(secondary_boot));
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+ if (!sku_rom_lut) {
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+ pr_warn("unable to ioremap SKU-ROM LUT register\n");
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+ return -ENOMEM;
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+ }
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+
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+ secondary_startup_phy = virt_to_phys(secondary_startup);
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+ BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
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+
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+ writel_relaxed(secondary_startup_phy, sku_rom_lut);
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+ /*
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+ * Ensure the write is visible to the secondary core.
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+ */
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+ smp_wmb();
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+
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+ iounmap(sku_rom_lut);
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+
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+ return 0;
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+}
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+
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+static void nsp_secondary_init(unsigned int cpu)
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+{
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+ /*
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+ * Let the primary cpu know we are out of holding pen.
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+ */
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+ write_pen_release(-1);
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+
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+ /*
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+ * Synchronise with the boot thread.
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+ */
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+ spin_lock(&boot_lock);
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+ spin_unlock(&boot_lock);
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+}
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+
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+static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
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+{
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+ static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
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+ struct device_node *node;
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+ int ret;
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+
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+ BUG_ON(secondary_boot); /* We're called only once */
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+
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+ /*
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|
+ * This function is only called via smp_ops->smp_prepare_cpu().
|
|
+ * That only happens if a "/cpus" device tree node exists
|
|
+ * and has an "enable-method" property that selects the SMP
|
|
+ * operations defined herein.
|
|
+ */
|
|
+ node = of_find_node_by_path("/cpus");
|
|
+ BUG_ON(!node);
|
|
+
|
|
+ /*
|
|
+ * Our secondary enable method requires a "secondary-boot-reg"
|
|
+ * property to specify a register address used to request the
|
|
+ * ROM code boot a secondary core. If we have any trouble
|
|
+ * getting this we fall back to uniprocessor mode.
|
|
+ */
|
|
+ if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
|
|
+ pr_warn("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
|
|
+ node->name);
|
|
+ ret = -ENOENT; /* Arrange to disable SMP */
|
|
+ goto out;
|
|
+ }
|
|
+
|
|
+ /*
|
|
+ * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
|
|
+ * returned, the SoC reported a uniprocessor configuration.
|
|
+ * We bail on any other error.
|
|
+ */
|
|
+ ret = scu_a9_enable();
|
|
+out:
|
|
+ of_node_put(node);
|
|
+ if (ret) {
|
|
+ /* Update the CPU present map to reflect uniprocessor mode */
|
|
+ pr_warn("disabling SMP\n");
|
|
+ init_cpu_present(&only_cpu_0);
|
|
+ }
|
|
+}
|
|
+
|
|
+/*
|
|
+ * The ROM code has the secondary cores looping, waiting for an event.
|
|
+ * When an event occurs each core examines the bottom two bits of the
|
|
+ * secondary boot register. When a core finds those bits contain its
|
|
+ * own core id, it performs initialization, including computing its boot
|
|
+ * address by clearing the boot register value's bottom two bits. The
|
|
+ * core signals that it is beginning its execution by writing its boot
|
|
+ * address back to the secondary boot register, and finally jumps to
|
|
+ * that address.
|
|
+ *
|
|
+ * So to start a core executing we need to:
|
|
+ * - Encode the (hardware) CPU id with the bottom bits of the secondary
|
|
+ * start address.
|
|
+ * - Write that value into the secondary boot register.
|
|
+ * - Generate an event to wake up the secondary CPU(s).
|
|
+ * - Wait for the secondary boot register to be re-written, which
|
|
+ * indicates the secondary core has started.
|
|
+ */
|
|
+static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|
+{
|
|
+ void __iomem *boot_reg;
|
|
+ phys_addr_t boot_func;
|
|
+ u64 start_clock;
|
|
+ u32 cpu_id;
|
|
+ u32 boot_val;
|
|
+ bool timeout = false;
|
|
+
|
|
+ cpu_id = cpu_logical_map(cpu);
|
|
+ if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
|
|
+ pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ if (!secondary_boot) {
|
|
+ pr_err("required secondary boot register not specified\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32));
|
|
+ if (!boot_reg) {
|
|
+ pr_err("unable to map boot register for cpu %u\n", cpu_id);
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+
|
|
+ /*
|
|
+ * Secondary cores will start in secondary_startup(),
|
|
+ * defined in "arch/arm/kernel/head.S"
|
|
+ */
|
|
+ boot_func = virt_to_phys(secondary_startup);
|
|
+ BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
|
|
+ BUG_ON(boot_func > (phys_addr_t)U32_MAX);
|
|
+
|
|
+ /* The core to start is encoded in the low bits */
|
|
+ boot_val = (u32)boot_func | cpu_id;
|
|
+ writel_relaxed(boot_val, boot_reg);
|
|
+
|
|
+ sev();
|
|
+
|
|
+ /* The low bits will be cleared once the core has started */
|
|
+ start_clock = local_clock();
|
|
+ while (!timeout && readl_relaxed(boot_reg) == boot_val)
|
|
+ timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;
|
|
+
|
|
+ iounmap(boot_reg);
|
|
+
|
|
+ if (!timeout)
|
|
+ return 0;
|
|
+
|
|
+ pr_err("timeout waiting for cpu %u to start\n", cpu_id);
|
|
+
|
|
+ return -ENXIO;
|
|
+}
|
|
+
|
|
+static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|
+{
|
|
+ unsigned long timeout;
|
|
+ int ret;
|
|
+
|
|
+ /*
|
|
+ * After wake up, secondary core branches to the startup
|
|
+ * address programmed at SKU ROM LUT location.
|
|
+ */
|
|
+ ret = nsp_write_lut(nsp_secondary_startup);
|
|
+ if (ret) {
|
|
+ pr_err("unable to write startup addr to SKU ROM LUT\n");
|
|
+ goto out;
|
|
+ }
|
|
+
|
|
+ /*
|
|
+ * The secondary processor is waiting to be released from
|
|
+ * the holding pen - release it, then wait for it to flag
|
|
+ * that it has been released by resetting pen_release.
|
|
+ */
|
|
+ spin_lock(&boot_lock);
|
|
+
|
|
+ write_pen_release(cpu_logical_map(cpu));
|
|
+ /*
|
|
+ * Send an Event to wake up the secondary core which is in
|
|
+ * WFE state. Updated pen_release should also be visible to
|
|
+ * the secondary core.
|
|
+ */
|
|
+ dsb_sev();
|
|
+
|
|
+ timeout = jiffies + (1 * HZ);
|
|
+ while (time_before(jiffies, timeout)) {
|
|
+ /* Make sure loads on other CPU is visible */
|
|
+ smp_rmb();
|
|
+ if (pen_release == -1)
|
|
+ break;
|
|
+
|
|
+ udelay(10);
|
|
+ }
|
|
+
|
|
+ spin_unlock(&boot_lock);
|
|
+
|
|
+ ret = pen_release != -1 ? -ENXIO : 0;
|
|
+
|
|
+out:
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static struct smp_operations bcm_smp_ops __initdata = {
|
|
+ .smp_prepare_cpus = bcm_smp_prepare_cpus,
|
|
+ .smp_boot_secondary = kona_boot_secondary,
|
|
+};
|
|
+CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
|
|
+ &bcm_smp_ops);
|
|
+
|
|
+struct smp_operations nsp_smp_ops __initdata = {
|
|
+ .smp_prepare_cpus = bcm_smp_prepare_cpus,
|
|
+ .smp_secondary_init = nsp_secondary_init,
|
|
+ .smp_boot_secondary = nsp_boot_secondary,
|
|
+};
|
|
+CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
|