mirror of https://github.com/hak5/openwrt-owl.git
40 lines
1.5 KiB
Diff
40 lines
1.5 KiB
Diff
From 5077ac38a86023124ebbe24cd1b7ecbd0f8edaff Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Tue, 3 May 2016 03:06:59 +0200
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Subject: [PATCH 086/102] net-next: mediatek: add next data pointer coherency
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protection
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The QDMA engine can fail to update the register pointing to the next TX
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descriptor if this bit does not get set in the QDMA configuration register.
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Not setting this bit can result in invalid values inside the TX rings
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registers which will causes TX stalls.
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Signed-off-by: Sean Wang <keyhaede@gmail.com>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +-
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 +
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2 files changed, 2 insertions(+), 1 deletion(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -1292,7 +1292,7 @@ static int mtk_start_dma(struct mtk_eth
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mtk_w32(eth,
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MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
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MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
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- MTK_RX_BT_32DWORDS,
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+ MTK_RX_BT_32DWORDS | MTK_NDP_CO_PRO,
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MTK_QDMA_GLO_CFG);
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return 0;
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -91,6 +91,7 @@
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#define MTK_QDMA_GLO_CFG 0x1A04
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#define MTK_RX_2B_OFFSET BIT(31)
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#define MTK_RX_BT_32DWORDS (3 << 11)
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+#define MTK_NDP_CO_PRO BIT(10)
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#define MTK_TX_WB_DDONE BIT(6)
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#define MTK_DMA_SIZE_16DWORDS (2 << 4)
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#define MTK_RX_DMA_BUSY BIT(3)
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