mirror of https://github.com/hak5/openwrt-owl.git
172 lines
4.4 KiB
Diff
172 lines
4.4 KiB
Diff
From 0c5476ab44aaffafcdce4885f09e86b300eb2241 Mon Sep 17 00:00:00 2001
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From: Lars-Peter Clausen <lars@metafoo.de>
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Date: Sat, 19 Jun 2010 04:08:11 +0000
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Subject: [PATCH] MIPS: JZ4740: Add power-management and system reset support
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Add support for suspend/resume and poweroff/reboot on a JZ4740 SoC.
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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Cc: linux-mips@linux-mips.org
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Cc: linux-kernel@vger.kernel.org
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Patchwork: https://patchwork.linux-mips.org/patch/1398/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/jz4740/pm.c | 56 ++++++++++++++++++++++++++++++++
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arch/mips/jz4740/reset.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++
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arch/mips/jz4740/reset.h | 6 +++
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3 files changed, 141 insertions(+), 0 deletions(-)
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create mode 100644 arch/mips/jz4740/pm.c
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create mode 100644 arch/mips/jz4740/reset.c
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create mode 100644 arch/mips/jz4740/reset.h
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--- /dev/null
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+++ b/arch/mips/jz4740/pm.c
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@@ -0,0 +1,56 @@
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+/*
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+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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+ * JZ4740 SoC power management support
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/pm.h>
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+#include <linux/delay.h>
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+#include <linux/suspend.h>
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+
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+#include <asm/mach-jz4740/clock.h>
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+
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+#include "clock.h"
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+#include "irq.h"
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+
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+static int jz4740_pm_enter(suspend_state_t state)
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+{
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+ jz4740_intc_suspend();
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+ jz4740_clock_suspend();
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+
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+ jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_SLEEP);
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+
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+ __asm__(".set\tmips3\n\t"
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+ "wait\n\t"
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+ ".set\tmips0");
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+
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+ jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_IDLE);
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+
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+ jz4740_clock_resume();
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+ jz4740_intc_resume();
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+
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+ return 0;
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+}
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+
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+static struct platform_suspend_ops jz4740_pm_ops = {
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+ .valid = suspend_valid_only_mem,
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+ .enter = jz4740_pm_enter,
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+};
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+
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+static int __init jz4740_pm_init(void)
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+{
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+ suspend_set_ops(&jz4740_pm_ops);
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+ return 0;
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+
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+}
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+late_initcall(jz4740_pm_init);
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--- /dev/null
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+++ b/arch/mips/jz4740/reset.c
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@@ -0,0 +1,79 @@
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+/*
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+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ */
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+
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+#include <linux/io.h>
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+#include <linux/kernel.h>
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+#include <linux/pm.h>
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+
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+#include <asm/reboot.h>
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+
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+#include <asm/mach-jz4740/base.h>
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+#include <asm/mach-jz4740/timer.h>
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+
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+static void jz4740_halt(void)
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+{
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+ while (1) {
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+ __asm__(".set push;\n"
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+ ".set mips3;\n"
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+ "wait;\n"
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+ ".set pop;\n"
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+ );
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+ }
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+}
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+
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+#define JZ_REG_WDT_DATA 0x00
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+#define JZ_REG_WDT_COUNTER_ENABLE 0x04
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+#define JZ_REG_WDT_COUNTER 0x08
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+#define JZ_REG_WDT_CTRL 0x0c
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+
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+static void jz4740_restart(char *command)
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+{
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+ void __iomem *wdt_base = ioremap(JZ4740_WDT_BASE_ADDR, 0x0f);
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+
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+ jz4740_timer_enable_watchdog();
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+
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+ writeb(0, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
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+
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+ writew(0, wdt_base + JZ_REG_WDT_COUNTER);
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+ writew(0, wdt_base + JZ_REG_WDT_DATA);
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+ writew(BIT(2), wdt_base + JZ_REG_WDT_CTRL);
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+
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+ writeb(1, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
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+ jz4740_halt();
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+}
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+
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+#define JZ_REG_RTC_CTRL 0x00
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+#define JZ_REG_RTC_HIBERNATE 0x20
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+
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+#define JZ_RTC_CTRL_WRDY BIT(7)
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+
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+static void jz4740_power_off(void)
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+{
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+ void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x24);
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+ uint32_t ctrl;
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+
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+ do {
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+ ctrl = readl(rtc_base + JZ_REG_RTC_CTRL);
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+ } while (!(ctrl & JZ_RTC_CTRL_WRDY));
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+
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+ writel(1, rtc_base + JZ_REG_RTC_HIBERNATE);
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+ jz4740_halt();
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+}
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+
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+void jz4740_reset_init(void)
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+{
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+ _machine_restart = jz4740_restart;
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+ _machine_halt = jz4740_halt;
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+ pm_power_off = jz4740_power_off;
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+}
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--- /dev/null
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+++ b/arch/mips/jz4740/reset.h
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@@ -0,0 +1,6 @@
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+#ifndef __MIPS_JZ4740_RESET_H__
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+#define __MIPS_JZ4740_RESET_H__
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+
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+extern void jz4740_reset_init(void);
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+
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+#endif
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