mirror of https://github.com/hak5/openwrt-owl.git
209 lines
7.2 KiB
Diff
209 lines
7.2 KiB
Diff
patches for bgmac backported from net-next/master
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--- a/drivers/net/ethernet/broadcom/Kconfig
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+++ b/drivers/net/ethernet/broadcom/Kconfig
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@@ -132,7 +132,8 @@ config BNX2X_SRIOV
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config BGMAC
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tristate "BCMA bus GBit core support"
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- depends on BCMA_HOST_SOC && HAS_DMA
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+ depends on BCMA_HOST_SOC && HAS_DMA && BCM47XX
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+ select PHYLIB
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---help---
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This driver supports GBit MAC and BCM4706 GBit MAC cores on BCMA bus.
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They can be found on BCM47xx SoCs and provide gigabit ethernet.
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--- a/drivers/net/ethernet/broadcom/bgmac.c
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+++ b/drivers/net/ethernet/broadcom/bgmac.c
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@@ -149,6 +149,8 @@ static netdev_tx_t bgmac_dma_tx_add(stru
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dma_desc->ctl0 = cpu_to_le32(ctl0);
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dma_desc->ctl1 = cpu_to_le32(ctl1);
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+ netdev_sent_queue(net_dev, skb->len);
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+
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wmb();
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/* Increase ring->end to point empty slot. We tell hardware the first
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@@ -157,6 +159,7 @@ static netdev_tx_t bgmac_dma_tx_add(stru
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if (++ring->end >= BGMAC_TX_RING_SLOTS)
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ring->end = 0;
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bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
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+ ring->index_base +
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ring->end * sizeof(struct bgmac_dma_desc));
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/* Always keep one slot free to allow detecting bugged calls. */
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@@ -177,10 +180,13 @@ static void bgmac_dma_tx_free(struct bgm
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struct device *dma_dev = bgmac->core->dma_dev;
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int empty_slot;
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bool freed = false;
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+ unsigned bytes_compl = 0, pkts_compl = 0;
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/* The last slot that hardware didn't consume yet */
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empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
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empty_slot &= BGMAC_DMA_TX_STATDPTR;
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+ empty_slot -= ring->index_base;
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+ empty_slot &= BGMAC_DMA_TX_STATDPTR;
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empty_slot /= sizeof(struct bgmac_dma_desc);
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while (ring->start != empty_slot) {
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@@ -192,6 +198,9 @@ static void bgmac_dma_tx_free(struct bgm
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slot->skb->len, DMA_TO_DEVICE);
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slot->dma_addr = 0;
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+ bytes_compl += slot->skb->len;
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+ pkts_compl++;
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+
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/* Free memory! :) */
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dev_kfree_skb(slot->skb);
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slot->skb = NULL;
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@@ -205,6 +214,8 @@ static void bgmac_dma_tx_free(struct bgm
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freed = true;
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}
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+ netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
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+
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if (freed && netif_queue_stopped(bgmac->net_dev))
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netif_wake_queue(bgmac->net_dev);
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}
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@@ -274,6 +285,8 @@ static int bgmac_dma_rx_read(struct bgma
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end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
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end_slot &= BGMAC_DMA_RX_STATDPTR;
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+ end_slot -= ring->index_base;
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+ end_slot &= BGMAC_DMA_RX_STATDPTR;
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end_slot /= sizeof(struct bgmac_dma_desc);
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ring->end = end_slot;
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@@ -418,9 +431,6 @@ static int bgmac_dma_alloc(struct bgmac
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ring = &bgmac->tx_ring[i];
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ring->num_slots = BGMAC_TX_RING_SLOTS;
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ring->mmio_base = ring_base[i];
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- if (bgmac_dma_unaligned(bgmac, ring, BGMAC_DMA_RING_TX))
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- bgmac_warn(bgmac, "TX on ring 0x%X supports unaligned addressing but this feature is not implemented\n",
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- ring->mmio_base);
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/* Alloc ring of descriptors */
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size = ring->num_slots * sizeof(struct bgmac_dma_desc);
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@@ -435,6 +445,13 @@ static int bgmac_dma_alloc(struct bgmac
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if (ring->dma_base & 0xC0000000)
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bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
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+ ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
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+ BGMAC_DMA_RING_TX);
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+ if (ring->unaligned)
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+ ring->index_base = lower_32_bits(ring->dma_base);
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+ else
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+ ring->index_base = 0;
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+
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/* No need to alloc TX slots yet */
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}
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@@ -444,9 +461,6 @@ static int bgmac_dma_alloc(struct bgmac
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ring = &bgmac->rx_ring[i];
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ring->num_slots = BGMAC_RX_RING_SLOTS;
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ring->mmio_base = ring_base[i];
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- if (bgmac_dma_unaligned(bgmac, ring, BGMAC_DMA_RING_RX))
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- bgmac_warn(bgmac, "RX on ring 0x%X supports unaligned addressing but this feature is not implemented\n",
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- ring->mmio_base);
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/* Alloc ring of descriptors */
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size = ring->num_slots * sizeof(struct bgmac_dma_desc);
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@@ -462,6 +476,13 @@ static int bgmac_dma_alloc(struct bgmac
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if (ring->dma_base & 0xC0000000)
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bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
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+ ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
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+ BGMAC_DMA_RING_RX);
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+ if (ring->unaligned)
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+ ring->index_base = lower_32_bits(ring->dma_base);
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+ else
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+ ring->index_base = 0;
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+
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/* Alloc RX slots */
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for (j = 0; j < ring->num_slots; j++) {
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err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
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@@ -489,12 +510,14 @@ static void bgmac_dma_init(struct bgmac
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for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
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ring = &bgmac->tx_ring[i];
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- /* We don't implement unaligned addressing, so enable first */
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- bgmac_dma_tx_enable(bgmac, ring);
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+ if (!ring->unaligned)
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+ bgmac_dma_tx_enable(bgmac, ring);
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bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
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lower_32_bits(ring->dma_base));
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bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
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upper_32_bits(ring->dma_base));
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+ if (ring->unaligned)
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+ bgmac_dma_tx_enable(bgmac, ring);
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ring->start = 0;
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ring->end = 0; /* Points the slot that should *not* be read */
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@@ -505,12 +528,14 @@ static void bgmac_dma_init(struct bgmac
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ring = &bgmac->rx_ring[i];
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- /* We don't implement unaligned addressing, so enable first */
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- bgmac_dma_rx_enable(bgmac, ring);
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+ if (!ring->unaligned)
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+ bgmac_dma_rx_enable(bgmac, ring);
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bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
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lower_32_bits(ring->dma_base));
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bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
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upper_32_bits(ring->dma_base));
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+ if (ring->unaligned)
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+ bgmac_dma_rx_enable(bgmac, ring);
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for (j = 0, dma_desc = ring->cpu_base; j < ring->num_slots;
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j++, dma_desc++) {
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@@ -531,6 +556,7 @@ static void bgmac_dma_init(struct bgmac
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}
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bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
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+ ring->index_base +
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ring->num_slots * sizeof(struct bgmac_dma_desc));
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ring->start = 0;
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@@ -908,10 +934,10 @@ static void bgmac_chip_reset(struct bgma
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struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
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u8 et_swtype = 0;
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u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
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- BGMAC_CHIPCTL_1_IF_TYPE_RMII;
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- char buf[2];
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+ BGMAC_CHIPCTL_1_IF_TYPE_MII;
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+ char buf[4];
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- if (bcm47xx_nvram_getenv("et_swtype", buf, 1) > 0) {
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+ if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
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if (kstrtou8(buf, 0, &et_swtype))
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bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
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buf);
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@@ -970,6 +996,8 @@ static void bgmac_chip_reset(struct bgma
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bgmac_miiconfig(bgmac);
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bgmac_phy_init(bgmac);
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+ netdev_reset_queue(bgmac->net_dev);
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+
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bgmac->int_status = 0;
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}
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--- a/drivers/net/ethernet/broadcom/bgmac.h
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+++ b/drivers/net/ethernet/broadcom/bgmac.h
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@@ -333,7 +333,7 @@
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#define BGMAC_CHIPCTL_1_IF_TYPE_MASK 0x00000030
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#define BGMAC_CHIPCTL_1_IF_TYPE_RMII 0x00000000
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-#define BGMAC_CHIPCTL_1_IF_TYPE_MI 0x00000010
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+#define BGMAC_CHIPCTL_1_IF_TYPE_MII 0x00000010
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#define BGMAC_CHIPCTL_1_IF_TYPE_RGMII 0x00000020
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#define BGMAC_CHIPCTL_1_SW_TYPE_MASK 0x000000C0
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#define BGMAC_CHIPCTL_1_SW_TYPE_EPHY 0x00000000
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@@ -384,6 +384,8 @@ struct bgmac_dma_ring {
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u16 mmio_base;
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struct bgmac_dma_desc *cpu_base;
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dma_addr_t dma_base;
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+ u32 index_base; /* Used for unaligned rings only, otherwise 0 */
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+ bool unaligned;
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struct bgmac_slot_info slots[BGMAC_RX_RING_SLOTS];
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};
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